[coreboot-gerrit] Patch set updated for coreboot: intel/apollolake: Correct the offsets in gnvs

[Furquan Shaikh (furquan@google.com)]

Furquan Shaikh (furquan at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15180

-gerrit

commit ee0601503f1287f0c152a86508c03ecaa3c0e3e3
Author: Furquan Shaikh <furquan at google.com>
Date:   Tue Jun 14 09:35:04 2016 -0700

    intel/apollolake: Correct the offsets in gnvs
    
    Offsets start from 0 instead of 1. Fix this in the gnvs definitions.
    
    BUG=chrome-os-partner:54342
    
    Change-Id: Id6766a8766ef430d19ffcb801bfab43d38de37db
    Signed-off-by: Furquan Shaikh <furquan at google.com>
---
 src/soc/intel/apollolake/acpi/globalnvs.asl | 12 ++++++------
 src/soc/intel/apollolake/include/soc/nvs.h  | 12 ++++++------
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index 1799f31..3597788 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -28,12 +28,12 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */
 	Offset (0x00),
-	PCNT,	8,      // 0x01 - Processor Count
-	PPCM,	8,      // 0x02 - Max PPC State
-	LIDS,	8,      // 0x03 - LID State
-	PWRS,	8,      // 0x04 - AC Power State
-	DPTE,	8,      // 0x05 - Enable DPTF
-	CBMC,	32,     // 0x06 - 0x09 - Coreboot Memory Console
+	PCNT,	8,      // 0x00 - Processor Count
+	PPCM,	8,      // 0x01 - Max PPC State
+	LIDS,	8,      // 0x02 - LID State
+	PWRS,	8,      // 0x03 - AC Power State
+	DPTE,	8,      // 0x04 - Enable DPTF
+	CBMC,	32,     // 0x05 - 0x08 - Coreboot Memory Console
 
 	/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
 	Offset (0x100),
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index a7ddf77..fda3556 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -28,12 +28,12 @@
 
 struct global_nvs_t {
 	/* Miscellaneous */
-	uint8_t	pcnt; /* 0x01 - Processor Count */
-	uint8_t	ppcm; /* 0x02 - Max PPC State */
-	uint8_t	lids; /* 0x03 - LID State */
-	uint8_t	pwrs; /* 0x04 - AC Power State */
-	uint8_t	dpte; /* 0x05 - Enable DPTF */
-	uint32_t	cbmc; /* 0x06 - 0x09 - Coreboot Memory Console */
+	uint8_t	pcnt; /* 0x00 - Processor Count */
+	uint8_t	ppcm; /* 0x01 - Max PPC State */
+	uint8_t	lids; /* 0x02 - LID State */
+	uint8_t	pwrs; /* 0x03 - AC Power State */
+	uint8_t	dpte; /* 0x04 - Enable DPTF */
+	uint32_t	cbmc; /* 0x05 - 0x08 - Coreboot Memory Console */
 	uint8_t	unused[247];
 
 	/* ChromeOS specific (0x100 - 0xfff) */