[coreboot-gerrit] New patch to review for coreboot: intel cache_as_ram: Fix typo in comment

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Fri Jun 17 20:18:38 CEST 2016


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15223

-gerrit

commit f69b2696e10ede2eb8f0be707c91e75611bc513b
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Fri Jun 17 07:54:36 2016 +0300

    intel cache_as_ram: Fix typo in comment
    
    Change-Id: I2539e490e160e01cab2ad8d2086d2f242a88c640
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/intel/haswell/cache_as_ram.inc            | 2 +-
 src/soc/intel/baytrail/romstage/cache_as_ram.inc  | 2 +-
 src/soc/intel/broadwell/romstage/cache_as_ram.inc | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index e09e74b..2ccef78 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -236,7 +236,7 @@ before_romstage:
 
 	post_code(0x38)
 
-	/* Setup stack as indicated by return value from ramstage_main(). */
+	/* Setup stack as indicated by return value from romstage_main(). */
 	movl	%ebx, %esp
 
 	/* Get number of MTRRs. */
diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc
index 4a1d31f..dcb6296 100644
--- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc
+++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc
@@ -217,7 +217,7 @@ before_romstage:
 
 	post_code(0x2e)
 
-	/* Setup stack as indicated by return value from ramstage_main(). */
+	/* Setup stack as indicated by return value from romstage_main(). */
 	movl	%ebx, %esp
 
 	/* Get number of MTRRs. */
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index a636e9f..20ef6e9 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -256,7 +256,7 @@ before_romstage:
 
 	post_code(0x38)
 
-	/* Setup stack as indicated by return value from ramstage_main(). */
+	/* Setup stack as indicated by return value from romstage_main(). */
 	movl	%ebx, %esp
 
 	/* Get number of MTRRs. */



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