[coreboot-gerrit] Patch set updated for coreboot: VIA C7 NANO: Fix early MTRR setting

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15238

-gerrit

commit c187dd054f7260d5cd60629b60b6cb0b0eb652fa
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Thu Jun 16 21:14:25 2016 +0300

    VIA C7 NANO: Fix early MTRR setting
    
    It would not be possible to set MTRR for range 1MiB to 4MiB.
    Our RAMTOP is power of 2 and enabling cache for bottom
    1MiB should cause no problems.
    
    Change-Id: I3619bc25be60f42b68615bfcdf36f02d66796e02
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/via/car/cache_as_ram.inc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 046d9c4..2f61b91 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -225,15 +225,15 @@ testok:
 	movl	$(MTRR_DEF_TYPE_EN), %eax
 	wrmsr
 
-	/* Enable caching for CONFIG_RAMBASE..CONFIG_RAMTOP. */
+	/* Enable caching for 0..CONFIG_RAMTOP. */
 	movl	$MTRR_PHYS_BASE(0), %ecx
 	xorl	%edx, %edx
-	movl	$(CONFIG_RAMBASE | MTRR_TYPE_WRBACK), %eax
+	movl	$(0x0 | MTRR_TYPE_WRBACK), %eax
 	wrmsr
 
 	movl	$MTRR_PHYS_MASK(0), %ecx
 	movl	$0x0000000f, %edx	/* AMD 40 bit 0xff */
-	movl	$(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRR_PHYS_MASK_VALID), %eax
+	movl	$(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
 	wrmsr
 
 	/* Cache XIP_ROM area to speedup coreboot code. */