[coreboot-gerrit] New patch to review for coreboot: With RELOCATABLE_RAMSTAGE ignore RAMTOP for MTRRs

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15249

-gerrit

commit e8406b951c5ad1853a7774c99906d5abaae58c71
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Wed Jun 15 15:58:06 2016 +0300

    With RELOCATABLE_RAMSTAGE ignore RAMTOP for MTRRs
    
    With RELOCATABLE_RAMSTAGE have write-back cache only
    for first 1MiB of RAM. A small part of this gets used
    during SMP initialisation before proper MTRR setup.
    
    Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/intel/haswell/romstage.c           |  4 ++--
 src/include/cpu/x86/mtrr.h                 | 15 +++++++++------
 src/soc/intel/baytrail/romstage/romstage.c |  4 ++--
 src/soc/intel/broadwell/romstage/stack.c   |  4 ++--
 4 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index c7e765a..11d449c 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -119,9 +119,9 @@ static void *setup_romstage_stack_after_car(void)
 	slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
 	num_mtrrs++;
 
-	/* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
+	/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
 	slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
-	slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
+	slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
 	slot = stack_push(slot, 0); /* upper base */
 	slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
 	num_mtrrs++;
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 4eb4f13..9ae8b0d 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -91,8 +91,15 @@ int get_free_var_mtrr(void);
 					(x>>6)|(x>>7)|(x>>8)|((1<<18)-1))
 #define _ALIGN_UP_POW2(x)	((x + _POW2_MASK(x)) & ~_POW2_MASK(x))
 
-#if !defined(CONFIG_RAMTOP) || !CONFIG_RAMTOP
-# error "CONFIG_RAMTOP not configured"
+#if CONFIG_RELOCATABLE_RAMSTAGE
+# define CACHE_TMP_RAMTOP (1<<20)
+#else
+# if !defined(CONFIG_RAMTOP) || !CONFIG_RAMTOP
+#  error "CONFIG_RAMTOP not configured"
+# endif
+# if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
+#  error "CONFIG_RAMTOP must be a power of 2"
+# endif
 #endif
 
 #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
@@ -122,8 +129,4 @@ int get_free_var_mtrr(void);
 
 #define CACHE_ROM_BASE	(((1<<20) - (CACHE_ROM_SIZE>>12))<<12)
 
-#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
-# error "CONFIG_RAMTOP must be a power of 2"
-#endif
-
 #endif /* CPU_X86_MTRR_H */
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 3668235..d3eea26 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -312,9 +312,9 @@ static void *setup_stack_and_mttrs(void)
 	slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
 	num_mtrrs++;
 
-	/* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
+	/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
 	slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
-	slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
+	slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
 	slot = stack_push(slot, 0); /* upper base */
 	slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
 	num_mtrrs++;
diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c
index 5c7a6e3..6c602a8 100644
--- a/src/soc/intel/broadwell/romstage/stack.c
+++ b/src/soc/intel/broadwell/romstage/stack.c
@@ -83,9 +83,9 @@ void *setup_stack_and_mttrs(void)
 	slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
 	num_mtrrs++;
 
-	/* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
+	/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
 	slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
-	slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
+	slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
 	slot = stack_push(slot, 0); /* upper base */
 	slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
 	num_mtrrs++;