[coreboot-gerrit] New patch to review for coreboot: SPD: fix DDR3 SDRAM memory module type

[HAOUAS Elyes (ehaouas@noos.fr)]

HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15262

-gerrit

commit 5db6aad3d42bfe4e778927b5b7774da8e7b6b96a
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Sun Jun 19 12:38:47 2016 +0200

    SPD: fix DDR3 SDRAM memory module type
    
    Fix 16B_SO_DIMM and 32B_SO_DIMM hex value
    
    Change-Id: I9210ac3409a4aaf55a0f6411d5960cfdca05068d
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 src/include/device/dram/ddr3.h | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index d58cdce..51c1e3d 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -14,6 +14,13 @@
  * GNU General Public License for more details.
  */
 
+/*
+ * JEDEC Standard No. 21-C
+ * Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM Modules 2014
+ * http://www.jedec.org/sites/default/files/docs/4_01_02_11R24.pdf
+ */
+
+
 #ifndef DEVICE_DRAM_DDR3L_H
 #define DEVICE_DRAM_DDR3L_H
 
@@ -78,8 +85,8 @@ enum spd_dimm_type {
 	SPD_DIMM_TYPE_72B_SO_RDIMM		= 0x09,
 	SPD_DIMM_TYPE_72B_SO_CDIMM		= 0x0a,
 	SPD_DIMM_TYPE_LRDIMM			= 0x0b,
-	SPD_DIMM_TYPE_16B_SO_DIMM		= 0x0d,
-	SPD_DIMM_TYPE_32B_SO_DIMM		= 0x0e,
+	SPD_DIMM_TYPE_16B_SO_DIMM		= 0x0c,
+	SPD_DIMM_TYPE_32B_SO_DIMM		= 0x0d,
 	/* Masks to bits 3:0 to give the dimm type */
 	SPD_DIMM_TYPE_MASK			= 0x0f,
 };