[coreboot-gerrit] Patch merged into coreboot/master: VIA C7 NANO: Fix early MTRR setting

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit d71cfd204109b66aef0fe233e1e78e3c840fed6d
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Thu Jun 16 21:14:25 2016 +0300

    VIA C7 NANO: Fix early MTRR setting
    
    It would not be possible to set MTRR for range 1MiB to 4MiB.
    Our RAMTOP is power of 2 and enabling cache for bottom
    1MiB should cause no problems.
    
    Change-Id: I3619bc25be60f42b68615bfcdf36f02d66796e02
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
    Reviewed-on: https://review.coreboot.org/15238
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/15238 for details.

-gerrit