[coreboot-gerrit] New patch to review for coreboot: SPD: Add DRAM Devices Types.

[HAOUAS Elyes (ehaouas@noos.fr)]

HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15265

-gerrit

commit 76af1dc1a3397005dbf2d57dd7bbaf414d1ca75a
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Mon Jun 20 18:57:19 2016 +0200

    SPD: Add DRAM Devices Types.
    
    Add SDRAM or Module Types to Byte 2.
    Use same modules type definitions in
    spd.h and spd_ddr2.h files.
    Use the right definitions in amdk8/raminit_f.c file.
    
    Change-Id: Id6e654a3a714c164bc9a7fbd9ab3e2f3c44ca5ea
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 src/include/spd.h                     |  4 +++
 src/include/spd_ddr2.h                | 20 +++++++++++---
 src/northbridge/amd/amdk8/raminit_f.c | 50 ++++++++++++++++++-----------------
 3 files changed, 47 insertions(+), 27 deletions(-)

diff --git a/src/include/spd.h b/src/include/spd.h
index 8f37ca9..8258b46 100644
--- a/src/include/spd.h
+++ b/src/include/spd.h
@@ -117,6 +117,10 @@ enum spd_memory_type {
 	SPD_MEMORY_TYPE_FBDIMM_DDR2		= 0x09,
 	SPD_MEMORY_TYPE_FB_PROBE_DDR2		= 0x0a,
 	SPD_MEMORY_TYPE_SDRAM_DDR3		= 0x0b,
+	SPD_MEMORY_TYPE_DDR4_SDRAM		= 0x0c,
+	SPD_MEMORY_TYPE_DDR4E_SDRAM		= 0x0e,
+	SPD_MEMORY_TYPE_LPDDR3_SDRAM		= 0x0f,
+	SPD_MEMORY_TYPE_LPDDR4_SDRAM		= 0x10,
 };
 
 /* SPD_MODULE_VOLTAGE values. */
diff --git a/src/include/spd_ddr2.h b/src/include/spd_ddr2.h
index a31b4aa..2fb90a8 100644
--- a/src/include/spd_ddr2.h
+++ b/src/include/spd_ddr2.h
@@ -15,9 +15,23 @@
  */
 
 /* SPDs for DDR2 SDRAM */
-#define SPD_MEM_TYPE	2
-	#define SPD_MEM_TYPE_SDRAM_DDR	0x07
-	#define SPD_MEM_TYPE_SDRAM_DDR2	0x08
+#define SPD_MEMORY_TYPE 2
+	#define SPD_MEMORY_TYPE_UNDEFINED		0x00
+	#define SPD_MEMORY_TYPE_FPM_DRAM		0x01
+	#define SPD_MEMORY_TYPE_EDO			0x02
+	#define SPD_MEMORY_TYPE_PIPELINED_NIBBLE	0x03
+	#define SPD_MEMORY_TYPE_SDRAM			0x04
+	#define SPD_MEMORY_TYPE_MULTIPLEXED_ROM		0x05
+	#define SPD_MEMORY_TYPE_SGRAM_DDR		0x06
+	#define SPD_MEMORY_TYPE_SDRAM_DDR		0x07
+	#define SPD_MEMORY_TYPE_SDRAM_DDR2		0x08
+	#define SPD_MEMORY_TYPE_FBDIMM_DDR2		0x09
+	#define SPD_MEMORY_TYPE_FB_PROBE_DDR2		0x0a
+	#define SPD_MEMORY_TYPE_SDRAM_DDR3		0x0b
+	#define SPD_MEMORY_TYPE_DDR4_SDRAM		0x0c
+	#define SPD_MEMORY_TYPE_DDR4E_SDRAM		0x0e
+	#define SPD_MEMORY_TYPE_LPDDR3_SDRAM		0x0f
+	#define SPD_MEMORY_TYPE_LPDDR4_SDRAM		0x10
 
 #define SPD_DIMM_TYPE	20	/* x  bit0 or bit4 =1 mean registered*/
 	#define SPD_DIMM_TYPE_RDIMM	(1<<0)
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index cd4b9fb..e97d22b 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -45,26 +45,26 @@
 	 and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
 	/*
 index:
-		[29: 0] DctOffset (Dram Controller Offset)
-		[30:30] DctAccessWrite (Dram Controller Read/Write Select)
-			0 = read access
-			1 = write access
-		[31:31] DctAccessDone (Dram Controller Access Done)
-			0 = Access in progress
-			1 = No access is progress
-
-		Data:
-		[31: 0] DctOffsetData (Dram Controller Offset Data)
-
-		Read:
-			- Write the register num to DctOffset with
-			  DctAccessWrite = 0
-			- poll the DctAccessDone until it = 1
-			- Read the data from DctOffsetData
-		Write:
-			- Write the data to DctOffsetData
-			- Write register num to DctOffset with DctAccessWrite = 1
-			- poll the DctAccessDone until it = 1
+	[29: 0] DctOffset (Dram Controller Offset)
+	[30:30] DctAccessWrite (Dram Controller Read/Write Select)
+		0 = read access
+		1 = write access
+	[31:31] DctAccessDone (Dram Controller Access Done)
+		0 = Access in progress
+		1 = No access is progress
+
+	Data:
+	[31: 0] DctOffsetData (Dram Controller Offset Data)
+
+	Read:
+		- Write the register num to DctOffset with
+		  DctAccessWrite = 0
+		- poll the DctAccessDone until it = 1
+		- Read the data from DctOffsetData
+	Write:
+		- Write the data to DctOffsetData
+		- Write register num to DctOffset with DctAccessWrite = 1
+		- poll the DctAccessDone until it = 1
 	*/
 
 
@@ -1391,8 +1391,9 @@ static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
 		device = ctrl->channel0[i];
 		printk_raminit("DIMM socket %i, channel 0 SPD device is 0x%02x\n", i, device);
 		if (device) {
-			byte = spd_read_byte(ctrl->channel0[i], SPD_MEM_TYPE);  /* Type */
-			if (byte == SPD_MEM_TYPE_SDRAM_DDR2) {
+			byte = spd_read_byte(ctrl->channel0[i],
+						SPD_MEMORY_TYPE);  /* Type */
+			if (byte == SPD_MEMORY_TYPE_SDRAM_DDR2) {
 				printk_raminit("\tDIMM detected\n");
 				dimm_mask |= (1 << i);
 			}
@@ -1400,8 +1401,9 @@ static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
 		device = ctrl->channel1[i];
 		printk_raminit("DIMM socket %i, channel 1 SPD device is 0x%02x\n", i, device);
 		if (device) {
-			byte = spd_read_byte(ctrl->channel1[i], SPD_MEM_TYPE);
-			if (byte == SPD_MEM_TYPE_SDRAM_DDR2) {
+			byte = spd_read_byte(ctrl->channel1[i],
+						SPD_MEMORY_TYPE);
+			if (byte == SPD_MEMORY_TYPE_SDRAM_DDR2) {
 				printk_raminit("\tDIMM detected\n");
 				dimm_mask |= (1 << (i + DIMM_SOCKETS));
 			}