[coreboot-gerrit] Patch set updated for coreboot: intel/lynxpoint, broadwell: Fix eDP display with Intel driver in Windows, Intel VBIOS in SeaBIOS payload and Intel GOP in Tianocore payload

[Prabal Saha (coolstarorganization@gmail.com)]

Prabal Saha (coolstarorganization at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15261

-gerrit

commit 65ff8756c1ce825e5194a977cca967a80bd8bdb5
Author: Prabal Saha <coolstarorganization at gmail.com>
Date:   Sat Jun 18 20:47:21 2016 -0700

    intel/lynxpoint,broadwell: Fix eDP display with Intel driver in Windows,
        Intel VBIOS in SeaBIOS payload and Intel GOP in Tianocore payload
    
    Test: Boot peppy and auron_paine to Windows with functional display
       in SeaBIOS. Install Intel HD Graphics driver with full video
       acceleration and internal display functional.
    
    
    Method Used for Debugging: Run Intel VBIOS in coreboot and move the line
       that runs the VBIOS to different parts of coreboot. Observed that
       eDP works if the VBIOS is run before the power optimizer lines and
       eDP is broken if the VBIOS is run after the power optimizer lines.
    
    Change-Id: I6d8252e3de396887c84533e355f41693b9ea7514
    Signed-off-by: Prabal Saha <coolstarorganization at gmail.com>
---
 src/soc/intel/broadwell/lpc.c         | 11 -----------
 src/southbridge/intel/lynxpoint/lpc.c |  7 -------
 2 files changed, 18 deletions(-)

diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 7e57b23..e49fe97 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -283,17 +283,6 @@ static const struct reg_script pch_pm_init_script[] = {
 	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b4, 0x00007001),
 	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3350, 0x022ddfff),
 	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001),
-	/* Power Optimizer */
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000),
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x08000080),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b10, 0x0000883c),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b14, 0x1e0a4616),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b24, 0x40000005),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b20, 0x0005db01),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a80, 0x05145005),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a84, 0x00001005),
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x2fff2fb1),
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00008000),
 	REG_SCRIPT_END
 };
 
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index f4c3826..e08906b 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -346,13 +346,6 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = {
 	RCBA_RMW_REG_32(0x33b4,  0, 0x00007001),
 	RCBA_RMW_REG_32(0x3350,  0, 0x022ddfff),
 	RCBA_RMW_REG_32(0x3354,  0, 0x00000001),
-	RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000),  /* Power Optimizer */
-	RCBA_RMW_REG_32(0x33c8, ~0, 0x08000080),  /* Power Optimizer */
-	RCBA_RMW_REG_32(0x2b10,  0, 0x0000883c),  /* Power Optimizer */
-	RCBA_RMW_REG_32(0x2b14,  0, 0x1e0a4616),  /* Power Optimizer */
-	RCBA_RMW_REG_32(0x2b24,  0, 0x40000005),  /* Power Optimizer */
-	RCBA_RMW_REG_32(0x2b20,  0, 0x0005db01),  /* Power Optimizer */
-	RCBA_RMW_REG_32(0x3a80,  0, 0x05145005),
 	RCBA_END_CONFIG
 };