[coreboot-gerrit] Patch set updated for coreboot: intel/apollolake: Add helper routine for spi reg read

[Furquan Shaikh (furquan@google.com)]

Furquan Shaikh (furquan at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15268

-gerrit

commit f651c3321cf82962a17e6108316e0b7b637be9b9
Author: Furquan Shaikh <furquan at google.com>
Date:   Sun Jun 19 23:20:08 2016 -0700

    intel/apollolake: Add helper routine for spi reg read
    
    BUG=chrome-os-partner:54563
    
    Change-Id: I56bc6b5292aec676103a436048abee8577edd961
    Signed-off-by: Furquan Shaikh <furquan at google.com>
---
 src/soc/intel/apollolake/include/soc/spi.h |  2 ++
 src/soc/intel/apollolake/spi.c             | 24 +++++++++++++++++-------
 2 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/src/soc/intel/apollolake/include/soc/spi.h b/src/soc/intel/apollolake/include/soc/spi.h
index 1414a84..f67110f 100644
--- a/src/soc/intel/apollolake/include/soc/spi.h
+++ b/src/soc/intel/apollolake/include/soc/spi.h
@@ -75,4 +75,6 @@
  */
 int spi_read_status(uint8_t *status);
 
+/* Read SPI controller register. */
+uint32_t spi_ctrlr_reg_read(uint16_t reg);
 #endif
diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c
index 58c566d..96d33de 100644
--- a/src/soc/intel/apollolake/spi.c
+++ b/src/soc/intel/apollolake/spi.c
@@ -64,14 +64,22 @@ static void _spi_get_ctx(struct spi_ctx *ctx)
 }
 
 /* Read register from the SPI controller. 'reg' is the register offset. */
-static uint32_t _spi_reg_read(struct spi_ctx *ctx, uint16_t reg)
+static uint32_t _spi_ctrlr_reg_read(struct spi_ctx *ctx, uint16_t reg)
 {
 	uintptr_t addr =  ALIGN_DOWN(ctx->mmio_base + reg, 4);
 	return read32((void *)addr);
 }
 
+uint32_t spi_ctrlr_reg_read(uint16_t reg)
+{
+	BOILERPLATE_CREATE_CTX(ctx);
+	return _spi_ctrlr_reg_read(ctx, reg);
+}
+
+
 /* Write to register in the SPI controller. 'reg' is the register offset. */
-static void _spi_reg_write(struct spi_ctx *ctx, uint16_t reg, uint32_t val)
+static void _spi_ctrlr_reg_write(struct spi_ctx *ctx, uint16_t reg,
+				      uint32_t val)
 {
 	uintptr_t addr =  ALIGN_DOWN(ctx->mmio_base + reg, 4);
 	write32((void *)addr, val);
@@ -92,8 +100,9 @@ static void _spi_reg_write(struct spi_ctx *ctx, uint16_t reg, uint32_t val)
 static uint32_t read_spi_sfdp_param(struct spi_ctx *ctx, uint16_t sfdp_reg)
 {
 	uint32_t ptinx_index = sfdp_reg & SPIBAR_PTINX_IDX_MASK;
-	_spi_reg_write(ctx, SPIBAR_PTINX, ptinx_index | SPIBAR_PTINX_HORD_JEDEC);
-	return _spi_reg_read(ctx, SPIBAR_PTDATA);
+	_spi_ctrlr_reg_write(ctx, SPIBAR_PTINX,
+				  ptinx_index | SPIBAR_PTINX_HORD_JEDEC);
+	return _spi_ctrlr_reg_read(ctx, SPIBAR_PTDATA);
 }
 
 /* Fill FDATAn FIFO in preparation for a write transaction. */
@@ -124,8 +133,9 @@ static void start_hwseq_xfer(struct spi_ctx *ctx, uint32_t hsfsts_cycle,
 	hsfsts |= hsfsts_cycle & SPIBAR_HSFSTS_FCYCLE_MASK;
 	hsfsts |= SPIBAR_HSFSTS_FBDC(len - 1);
 
-	_spi_reg_write(ctx, SPIBAR_FADDR, flash_addr);
-	_spi_reg_write(ctx, SPIBAR_HSFSTS_CTL, hsfsts | SPIBAR_HSFSTS_FGO);
+	_spi_ctrlr_reg_write(ctx, SPIBAR_FADDR, flash_addr);
+	_spi_ctrlr_reg_write(ctx, SPIBAR_HSFSTS_CTL,
+			     hsfsts | SPIBAR_HSFSTS_FGO);
 }
 
 static void print_xfer_error(struct spi_ctx *ctx, const char *failure_reason,
@@ -140,7 +150,7 @@ static int wait_for_hwseq_xfer(struct spi_ctx *ctx)
 {
 	uint32_t hsfsts;
 	do {
-		hsfsts = _spi_reg_read(ctx, SPIBAR_HSFSTS_CTL);
+		hsfsts = _spi_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL);
 
 		if (hsfsts & SPIBAR_HSFSTS_FCERR) {
 			ctx->hsfsts_on_last_error = hsfsts;