[coreboot-gerrit] New patch to review for coreboot: intel/apollolake: Disable setting of EISS bit in FSP

[Furquan Shaikh (furquan@google.com)]

Furquan Shaikh (furquan at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15276

-gerrit

commit bf444dd59cafa7bc19e7f83c8991f878629e61a2
Author: Furquan Shaikh <furquan at google.com>
Date:   Mon Jun 20 16:08:42 2016 -0700

    intel/apollolake: Disable setting of EISS bit in FSP
    
    chrome-os-partner:54589
    
    Change-Id: I5bdd417ed2f7ec013aeb8a0d4a9de57b1ad564a1
    Signed-off-by: Furquan Shaikh <furquan at google.com>
---
 src/soc/intel/apollolake/chip.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 4fa4ce4..dd4a0a5 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -138,6 +138,9 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
 	silconfig->P2sbBase = P2SB_BAR;
 
 	silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
+
+	/* Disable setting of EISS bit in FSP. */
+	silconfig->SpiEiss = 0;
 }
 
 struct chip_operations soc_intel_apollolake_ops = {