[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake: Add utility functions for global reset

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15278

-gerrit

commit 68d52ecbc3ee68df31fe5722aebfebd2715c5961
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Fri Jun 17 15:30:13 2016 -0700

    soc/intel/apollolake: Add utility functions for global reset
    
    Apollolake defines Global Reset where Host, TXE and PMC are reset.
    During boot we may need to trigger a global reset as part of platform
    initialization (or for error handling). Define functions to trigger
    global reset, enable/disable it and lock global reset bit.
    
    BUG=chrome-os-partner:54149
    BRANCH=none
    TEST=none
    
    Change-Id: I296bba89930c640a1061e7c7fb31c7803080bb03
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/include/soc/pm.h    |  7 +++++++
 src/soc/intel/apollolake/include/soc/reset.h | 24 +++++++++++++++++++++
 src/soc/intel/apollolake/pmutil.c            | 31 ++++++++++++++++++++++++++++
 src/soc/intel/apollolake/reset.c             | 10 ++++++++-
 4 files changed, 71 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 856872e..7c8171e 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -128,6 +128,10 @@
 #define GEN_PMCON2		0x1024
 #       define RPS		(1 <<  2)
 #define GEN_PMCON3		0x1028
+#define ETR			0x1048
+#	define CF9_LOCK		(1 << 31)
+#	define CF9_GLB_RST	(1 << 20)
+
 
 /* Generic sleep state types */
 #define SLEEP_STATE_S0		0
@@ -168,4 +172,7 @@ void enable_gpe(uint32_t mask);
 void disable_gpe(uint32_t mask);
 void disable_all_gpe(void);
 
+void global_reset_enable(uint8_t enable);
+void global_reset_lock(void);
+
 #endif
diff --git a/src/soc/intel/apollolake/include/soc/reset.h b/src/soc/intel/apollolake/include/soc/reset.h
new file mode 100644
index 0000000..3049aef
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/reset.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_APOLLOLAKE_RESET_H_
+#define _SOC_APOLLOLAKE_RESET_H_
+
+#include <reset.h>
+
+void global_reset(void);
+
+#endif
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index 6e47911..73dc9e6 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -365,3 +365,34 @@ int vboot_platform_is_resuming(void)
 	typ = (inl(ACPI_PMIO_BASE + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT;
 	return typ == SLP_TYP_S3;
 }
+
+/*
+ * If possible, lock 0xcf9. Once the register is locked, it can't be changed.
+ * This lock is reset on cold boot, hard reset, soft reset and Sx.
+ */
+void global_reset_lock(void)
+{
+	uintptr_t etr = read_pmc_mmio_bar() + ETR;
+	uint32_t reg;
+
+	reg = read32((void *)etr);
+	if (reg & CF9_LOCK)
+		return;
+	reg |= CF9_LOCK;
+	write32((void *)etr, reg);
+}
+
+/*
+ * Enable or disable global reset. If global reset is enabled, hard reset and
+ * soft reset will trigger global reset, where both host and TXE are reset.
+ * This is cleared on cold boot, hard reset, soft reset and Sx.
+ */
+void global_reset_enable(uint8_t enable)
+{
+	uintptr_t etr = read_pmc_mmio_bar() + ETR;
+	uint32_t reg;
+
+	reg = read32((void *)etr);
+	reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST;
+	write32((void *)etr, reg);
+}
diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c
index eb43c41..d9a97a4 100644
--- a/src/soc/intel/apollolake/reset.c
+++ b/src/soc/intel/apollolake/reset.c
@@ -18,7 +18,8 @@
 #include <arch/hlt.h>
 #include <arch/io.h>
 #include <halt.h>
-#include <reset.h>
+#include <soc/pm.h>
+#include <soc/reset.h>
 
 /* Reset control port */
 #define RST_CNT			0xcf9
@@ -48,3 +49,10 @@ void cpu_reset(void)
 	outb(RST_CPU, RST_CNT);
 	halt();
 }
+
+void global_reset(void)
+{
+	global_reset_enable(1);
+	hard_reset();
+	halt();
+}