[coreboot-gerrit] Patch set updated for coreboot: intel/apollolake/spi: Add support for reading status reg

[Furquan Shaikh (furquan@google.com)]

Furquan Shaikh (furquan at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15266

-gerrit

commit 3912c5a5015d3311f4d4ac1ff8231e6520c893b8
Author: Furquan Shaikh <furquan at google.com>
Date:   Fri Jun 17 15:50:24 2016 -0700

    intel/apollolake/spi: Add support for reading status reg
    
    spi_read_status reads the status register using hardware sequencing and
    returns 0 on success and -1 on error. Use spi_read_status to return
    appropriate value for get_sw_write_protect.
    
    BUG=chrome-os-partner:54283
    
    Change-Id: I7650b5c0ab05a8429c2b291f00d4672446d86e03
    Signed-off-by: Furquan Shaikh <furquan at google.com>
---
 src/soc/intel/apollolake/Makefile.inc      |  1 +
 src/soc/intel/apollolake/include/soc/spi.h |  7 +++++++
 src/soc/intel/apollolake/romstage.c        | 10 ++++++++++
 src/soc/intel/apollolake/spi.c             | 13 +++++++++++++
 4 files changed, 31 insertions(+)

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index a840ad5..a7596e4 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -30,6 +30,7 @@ romstage-y += mmap_boot.c
 romstage-y += tsc_freq.c
 romstage-y += pmutil.c
 romstage-y += reset.c
+romstage-y += spi.c
 
 smm-y += mmap_boot.c
 smm-y += pmutil.c
diff --git a/src/soc/intel/apollolake/include/soc/spi.h b/src/soc/intel/apollolake/include/soc/spi.h
index 52ea770..1414a84 100644
--- a/src/soc/intel/apollolake/include/soc/spi.h
+++ b/src/soc/intel/apollolake/include/soc/spi.h
@@ -59,6 +59,7 @@
 #define  SPIBAR_HSFSTS_CYCLE_WRITE	SPIBAR_HSFSTS_FCYCLE(2)
 #define  SPIBAR_HSFSTS_CYCLE_4K_ERASE	SPIBAR_HSFSTS_FCYCLE(3)
 #define  SPIBAR_HSFSTS_CYCLE_64K_ERASE	SPIBAR_HSFSTS_FCYCLE(4)
+#define  SPIBAR_HSFSTS_CYCLE_RD_STATUS	SPIBAR_HSFSTS_FCYCLE(8)
 
 /* Bit definitions for PTINX register */
 #define  SPIBAR_PTINX_COMP_0		(0 << 14)
@@ -68,4 +69,10 @@
 #define  SPIBAR_PTINX_HORD_JEDEC	(2 << 12)
 #define  SPIBAR_PTINX_IDX_MASK		0xffc
 
+/*
+ * Reads status register. On success returns 0 and status contains the value
+ * read from the status register. On error returns -1.
+ */
+int spi_read_status(uint8_t *status);
+
 #endif
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 756e275..0c8f1c2 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -21,6 +21,7 @@
 #include <arch/io.h>
 #include <arch/symbols.h>
 #include <assert.h>
+#include <bootmode.h>
 #include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -37,6 +38,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
+#include <soc/spi.h>
 #include <soc/uart.h>
 #include <string.h>
 #include <timestamp.h>
@@ -260,3 +262,11 @@ void mainboard_memory_init_params(struct FSPM_UPD *mupd)
 {
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }
+
+int get_sw_write_protect_state(void)
+{
+	uint8_t status;
+
+	/* Return unprotected status if status read fails. */
+	return spi_read_status(&status) ? 0 : !!(status & 0x80);
+}
diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c
index 469bb9e..58c566d 100644
--- a/src/soc/intel/apollolake/spi.c
+++ b/src/soc/intel/apollolake/spi.c
@@ -373,3 +373,16 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
 
 	return slave;
 }
+
+int spi_read_status(uint8_t *status)
+{
+	BOILERPLATE_CREATE_CTX(ctx);
+
+	if (exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0,
+				 sizeof(*status)) != SUCCESS)
+		return -1;
+
+	drain_xfer_fifo(ctx, status, sizeof(*status));
+
+	return 0;
+}