[coreboot-gerrit] New patch to review for coreboot: arch/riscv: Show fault PC and load address on load access faults

[Jonathan Neuschäfer (j.neuschaefer@gmx.net)]

Jonathan Neuschäfer (j.neuschaefer at gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15286

-gerrit

commit e2dbe2842c1a4b25a97ecf6ef9dbe5fc1f4b38be
Author: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Date:   Tue Jun 21 19:37:03 2016 +0200

    arch/riscv: Show fault PC and load address on load access faults
    
    Change-Id: Ib0535bf25ce25550cc17f64177f804a70aa13fb3
    Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
 src/arch/riscv/trap_handler.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index ff3be56..5b4d0b1 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -122,6 +122,8 @@ void trap_handler(trapframe *tf) {
 			break;
 		case 5:
 			printk(BIOS_DEBUG, "Trap: Load access fault\n");
+			printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc);
+			printk(BIOS_DEBUG, "Load Address: %p\n", badAddr);
 			break;
 		case 6:
 			printk(BIOS_DEBUG, "Trap: Store address misaligned\n");