[coreboot-gerrit] Patch set updated for coreboot: mainboard/intel/amenia: Use common NHLT
Saurabh Satija (saurabh.satija@intel.com)
gerrit at coreboot.org
Wed Jun 22 05:00:00 CEST 2016
Saurabh Satija (saurabh.satija at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15024
-gerrit
commit 501c9af16e2878e20522e90e046ebf660ef4db68
Author: Saurabh Satija <saurabh.satija at intel.com>
Date: Thu May 26 16:08:45 2016 -0700
mainboard/intel/amenia: Use common NHLT
Add ACPI NHLT table generation that the current hardware
supports.
Amenia has support for audio codecs, Nuvoton for headsets and
Maxim for speakers.
Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9
Signed-off-by: Saurabh Satija <saurabh.satija at intel.com>
---
src/mainboard/intel/amenia/Kconfig | 8 +++
src/mainboard/intel/amenia/dsdt.asl | 11 ++--
src/mainboard/intel/amenia/mainboard.c | 91 +++++++++++++++++++++++++++++++++-
3 files changed, 103 insertions(+), 7 deletions(-)
diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig
index 6dd171c..6be5151 100644
--- a/src/mainboard/intel/amenia/Kconfig
+++ b/src/mainboard/intel/amenia/Kconfig
@@ -14,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_CHROMEOS
select SYSTEM_TYPE_LAPTOP
select TPM_ON_FAST_SPI
+ select ACPI_NHLT
+ select USE_COMMON_AUDIO
config CHROMEOS
bool
@@ -52,4 +54,10 @@ config MAX_CPUS
int
default 8
+config INCLUDE_AUDIO_BLOBS
+ bool "Include blobs for audio."
+ select AUDIO_DMIC_2CH_16B
+ select AUDIO_SPEAKER_RENDER
+ select AUDIO_HEADSET
+
endif # BOARD_INTEL_AMENIA
diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl
index 4a64f87..46404ed 100644
--- a/src/mainboard/intel/amenia/dsdt.asl
+++ b/src/mainboard/intel/amenia/dsdt.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2016 Intel Corp.
* (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@@ -33,15 +33,16 @@ DefinitionBlock(
Scope (\_SB) {
Device (PCI0)
{
- #include <soc/intel/apollolake/acpi/northbridge.asl>
- #include <soc/intel/apollolake/acpi/southbridge.asl>
+ #include <soc/intel/apollolake/acpi/northbridge.asl>
+ #include <soc/intel/apollolake/acpi/southbridge.asl>
+ #include <soc/intel/apollolake/acpi/pch_hda.asl>
}
}
/* Mainboard Specific devices */
#include "acpi/mainboard.asl"
- /* Chipset specific sleep states */
- #include <soc/intel/apollolake/acpi/sleepstates.asl>
+ /* Chipset specific sleep states */
+ #include <soc/intel/apollolake/acpi/sleepstates.asl>
#include "acpi/superio.asl"
}
diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c
index 22304f8..fbf522b 100644
--- a/src/mainboard/intel/amenia/mainboard.c
+++ b/src/mainboard/intel/amenia/mainboard.c
@@ -16,8 +16,13 @@
*/
#include <device/device.h>
+#include <drivers/intel/audio/audio.h>
+#include <arch/acpi.h>
+#include <console/console.h>
#include <soc/gpio.h>
#include <soc/pci_devs.h>
+#include <stdlib.h>
+#include <string.h>
#include "ec.h"
/* TODO: Move GPIO config to its own file once we get more GPIOs in the list */
@@ -89,7 +94,6 @@ static const struct pad_config amenia_gpios[] = {
PAD_CFG_GPO(GPIO_154, 1, DEEP), /* BT_DISABLE_1P8_N */
PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* DB_ID */
-
PAD_CFG_NF(GPIO_172, UP_20K, DEEP, NF1), /* SDCARD_CLK */
PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */
PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */
@@ -100,7 +104,6 @@ static const struct pad_config amenia_gpios[] = {
PAD_CFG_NF(GPIO_179, NATIVE, DEEP, NF1), /* SDCARD_CLK_FB */
PAD_CFG_GPO(GPIO_183, 1, DEEP), /* SDCARD_PWR_EN_N */
-
/* Configure eMMC pins for proper pull UP/DN */
PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC0_CLK */
PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC0_D0 */
@@ -129,7 +132,44 @@ static const struct pad_config amenia_gpios[] = {
PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */
PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */
PAD_CFG_NF(PMC_SPI_FS1, NATIVE, DEEP, NF2), /* HV_DDI2_HPD */
+};
+
+static const struct nhlt_format_config dmic_2ch_cfg[] = {
+ /* 48 KHz 16-bits per sample. */
+ {
+ .num_channels = 2,
+ .sample_freq_khz = 48,
+ .container_bits_per_sample = 16,
+ .valid_bits_per_sample = 16,
+ .settings_file = "dmic-2ch-48khz-16b.bin",
+ },
+};
+
+static const struct nhlt_format_config headset_cfg[] = {
+ /* 48 KHz 24-bits per sample. */
+ {
+ .num_channels = 2,
+ .sample_freq_khz = 48,
+ .container_bits_per_sample = 32,
+ .valid_bits_per_sample = 24,
+ .settings_file = "headset.bin",
+ },
+};
+
+static struct nhlt_tdm_config headset_tdm_cfg = {
+ .virtual_slot = 0,
+ .config_type = NHLT_TDM_BASIC,
+};
+static const struct nhlt_format_config speaker_cfg[] = {
+ /* 48 KHz 24-bits per sample. */
+ {
+ .num_channels = 2,
+ .sample_freq_khz = 48,
+ .container_bits_per_sample = 32,
+ .valid_bits_per_sample = 24,
+ .settings_file = "speaker-render.bin",
+ },
};
static void mainboard_init(void *chip_info)
@@ -138,6 +178,53 @@ static void mainboard_init(void *chip_info)
mainboard_ec_init();
}
+static unsigned long mainboard_write_acpi_tables(
+ device_t device, unsigned long current, acpi_rsdp_t *rsdp)
+{
+ uintptr_t start_addr;
+ uintptr_t end_addr;
+ struct nhlt *nhlt;
+
+ start_addr = current;
+
+ nhlt = nhlt_init();
+
+ if (nhlt == NULL)
+ return start_addr;
+
+ /* 2 Channel DMIC array. */
+ if (nhlt_soc_add_dmic_array(nhlt, 2, dmic_2ch_cfg, ARRAY_SIZE(dmic_2ch_cfg)))
+ printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
+
+ /* Dialog for Headset codec.
+ * Headset codec is bi-directional but uses the same configuration settings
+ * for render and capture endpoints.
+ */
+ if (nhlt_soc_add_codec_on_ssp(nhlt, headset_cfg, ARRAY_SIZE(headset_cfg), headset_cfg,
+ ARRAY_SIZE(headset_cfg), &headset_tdm_cfg, AUDIO_LINK_SSP1, AUDIO_BIDIR))
+ printk(BIOS_ERR, "Couldn't add headset codec.\n");
+
+ /* MAXIM Smart Amps for left and right speakers. This is Render only, capture
+ * cfg can be NULL.
+ */
+ if (nhlt_soc_add_codec_on_ssp(nhlt, speaker_cfg, ARRAY_SIZE(speaker_cfg), NULL, 0,
+ NULL, AUDIO_LINK_SSP5, AUDIO_RENDER))
+ printk(BIOS_ERR, "Couldn't add speaker codec.\n");
+
+ end_addr = nhlt_soc_serialize(nhlt, start_addr);
+
+ if (end_addr != start_addr)
+ acpi_add_table(rsdp, (void *)start_addr);
+
+ return end_addr;
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->write_acpi_tables = (void *) mainboard_write_acpi_tables;
+}
+
struct chip_operations mainboard_ops = {
.init = mainboard_init,
+ .enable_dev = mainboard_enable,
};
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