[coreboot-gerrit] Patch set updated for coreboot: [NotForMerge]Northbridge/i945 fix fsbclk function.

[HAOUAS Elyes (ehaouas@noos.fr)]

HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14456

-gerrit

commit 92d3ab7f6f5adfc1d12842a895ad747ef8f2e162
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Thu Apr 21 22:14:51 2016 +0200

    [NotForMerge]Northbridge/i945 fix fsbclk function.
    
    I believe that fsbclk value for i945M  is wrong.
    I think , that this value should be equal to MSR_FSB_FREQ.
    So , regarding the document
    “64-ia-32-architectures-software-developer-manual-325462.pdf",
    to MSR_FSB_FREQ = 0 means FSB 1066.
    I think that i945m datasheet is wrong:
    Page 111 they said:
    "FSB Capability:
    011:(G)MCH capable of up to FSB 667
    100: (G)MCH capable of up to FSB 533
    Others: Reserved
    These values are determined by the BSEL [2:0] frequency
    straps. Any unsupported straps will render the (G)MCH host
    interface inoperable."
    And page 166:
    "FSB Frequency Select:
    Reflects the State of BSEL pins from the Processor. BSEL(2:0)
    selects the FSB frequency as defined below.
    000: FSB400
    001: FSB533
    011: FSB667
    Others: Reserved
    Attempts to strap values to unsupported frequencies will shut
    down the host PLL."
    For both cases, the value is determined by the BSEL pins from
    the processor MSR_FSB_FREQ.
    
    Change-Id: I7dcdc641d647b45a086098a316043883d0b3fefb
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 src/northbridge/intel/i945/raminit.c | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 59a31de..a8cf2e3 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -119,29 +119,29 @@ static int memclk(void)
 	return -1;
 }
 
-#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
-static u16 fsbclk(void)
-{
-	switch (MCHBAR32(CLKCFG) & 7) {
-	case 0: return 400;
-	case 1: return 533;
-	case 3: return 667;
-	default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
-	}
-	return 0xffff;
-}
-#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
 static u16 fsbclk(void)
 {
 	switch (MCHBAR32(CLKCFG) & 7) {
-	case 0: return 1066;
-	case 1: return 533;
-	case 2: return 800;
+	/* should be equal to MSR_FSB_FREQ */
+	case 0:
+		#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
+			return 400; // seems to be wrong
+		#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
+			return 1066; // 266.67 MHz should be utilized if
+				// performing calculation with System Bus Speed
+		#endif
+	case 1: return 533; // 133.33 MHz
+	case 2: return 800; // 200 MHz
+	case 3: return 667; // 166.67 MHz
+	case 4: return 1333; // 333.33 MHz
+	case 5: return 400; // 100 MHz
+	case 6: return 1600; // 400 MHz
+	case 7: return 333; // 83 MHz
+
 	default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 	}
 	return 0xffff;
 }
-#endif
 
 static int sdram_capabilities_max_supported_memory_frequency(void)
 {