[coreboot-gerrit] New patch to review for coreboot: intel/amenia: GPE routing for amenia

[Shaunak Saha (shaunak.saha@intel.com)]

Shaunak Saha (shaunak.saha at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15325

-gerrit

commit ef98706f5ea612cff43795a70a6d4c8115bc1525
Author: Shaunak Saha <shaunak.saha at intel.com>
Date:   Fri Jun 10 19:36:49 2016 -0700

    intel/amenia: GPE routing for amenia
    
    This patch sets the devicetree for gpe0_dw configuration
    and also confgigures the GPIO lines for SCI.EC_SCI_GPI
    is set to proper value and the gpio_tier1_sci_en bit in acpi
    rgister is set by adding a dummy method in GPE scope.
    
    BUG = 53438
    TEST = Toogle pch_sci_l from ec console using gpioset command
           and see that the sci counter increases in /sys/firmware/acpi/interrupt
            and also 9 in /proc/interrupt
    
    Change-Id: I3ae9ef7c6a3c8688bcb6cb4c73f5618e7cde342c
    Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
 src/mainboard/intel/amenia/acpi/mainboard.asl | 6 ++++++
 src/mainboard/intel/amenia/devicetree.cb      | 8 ++++++++
 src/mainboard/intel/amenia/ec.h               | 5 ++---
 src/mainboard/intel/amenia/mainboard.c        | 4 ++--
 4 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/intel/amenia/acpi/mainboard.asl b/src/mainboard/intel/amenia/acpi/mainboard.asl
index a679471..535360a 100644
--- a/src/mainboard/intel/amenia/acpi/mainboard.asl
+++ b/src/mainboard/intel/amenia/acpi/mainboard.asl
@@ -117,3 +117,9 @@ Scope (\_SB.PCI0.LPCB)
 	#include <drivers/pc80/tpm/acpi/tpm.asl>
 	#include "ec.asl"
 }
+
+Scope(\_GPE)
+{
+	/* Dummy method for the Tier 1 GPIO SCI enable bit */
+	Method(_L0F, 0) {}
+}
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb
index 8128c71..14812df 100644
--- a/src/mainboard/intel/amenia/devicetree.cb
+++ b/src/mainboard/intel/amenia/devicetree.cb
@@ -15,6 +15,14 @@ chip soc/intel/apollolake
 	# 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200
 	register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required
 
+	# GPE configuration
+        # Note that GPE events called out in ASL code rely on this
+        # route. i.e. If this route changes then the affected GPE
+        # offset bits also need to be changed.
+        register "gpe0_dw1" = "GPP_6"
+        register "gpe0_dw2" = "GPP_7"
+        register "gpe0_dw3" = "GPP_0"
+
 	device domain 0 on
 		device pci 00.0 on end	# - Host Bridge
 		device pci 00.1 on end	# - DPTF
diff --git a/src/mainboard/intel/amenia/ec.h b/src/mainboard/intel/amenia/ec.h
index 91890fd..d102715 100644
--- a/src/mainboard/intel/amenia/ec.h
+++ b/src/mainboard/intel/amenia/ec.h
@@ -20,9 +20,8 @@
 
 #include <ec/google/chromeec/ec_commands.h>
 
-/* This is the GPE status bit.
-   TODO: Fix this to proper bit matching GPE routing table */
-#define EC_SCI_GPI   15
+/*32 from GPE0a which is reserved + GPIO_11 for SCI*/
+#define EC_SCI_GPI   43
 
 #define MAINBOARD_EC_SCI_EVENTS \
 	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c
index 22304f8..38c3c8f 100644
--- a/src/mainboard/intel/amenia/mainboard.c
+++ b/src/mainboard/intel/amenia/mainboard.c
@@ -29,11 +29,11 @@ static const struct pad_config amenia_gpios[] = {
 	PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1),	/* PANEL0_BKLTCTL */
 
 	PAD_CFG_GPI(GPIO_9, UP_20K, DEEP),		/* SPI_TPM_IRQ_N  */
-	PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, LEVEL, NONE),	/* SOC_WAKE_SCI_N */
+	PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, EDGE_SINGLE, NONE),	/* SOC_WAKE_SCI_N */
 	PAD_CFG_GPI_APIC(GPIO_18, UP_20K, DEEP, LEVEL, NONE),	/* Trackpad_INT_N */
 	PAD_CFG_GPI_APIC(GPIO_19, UP_20K, DEEP, LEVEL, NONE),	/* Audio_Jack_Present_N */
 	PAD_CFG_GPI_APIC(GPIO_21, UP_20K, DEEP, LEVEL, NONE),	/* TCH_INT_N */
-	PAD_CFG_GPI_APIC(GPIO_22, UP_20K, DEEP, LEVEL, NONE),	/* EC_SOC_WAKE_1P8_N */
+	PAD_CFG_GPI_SCI(GPIO_22, UP_20K, DEEP, EDGE_SINGLE, NONE),	/* EC_SOC_WAKE_1P8_N */
 	PAD_CFG_GPO(GPIO_23, 1, DEEP),			/* GPS_NSTANDBY */
 	PAD_CFG_GPO(GPIO_24, 1, DEEP),			/* SSD_SATA_DEVSLP */
 	PAD_CFG_GPI_APIC(GPIO_30, UP_20K, DEEP, LEVEL, NONE),	/* EC_KBD_IRQ_SOC_N */