[coreboot-gerrit] Patch merged into coreboot/master: rockchip/rk3399: correct sdram inc file DENALI_CTL_217_DATA value

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 203fe7278ae2521edcaeda96740bcc5ffa36cbdd
Author: Lin Huang <hl at rock-chips.com>
Date:   Thu Jun 16 10:39:10 2016 +0800

    rockchip/rk3399: correct sdram inc file DENALI_CTL_217_DATA value
    
    for per cs training, there should be more cycles to switch delay line.
    so increase W2W_DIFFCS_DLY_F0 value from 0x1 to 0x5.
    
    BRANCH=none
    BUG=chrome-os-partner:54144
    TEST=run "stressapptest -M 1024 -s 1000" and pass
    
    Change-Id: I11720b7c6f009789b88ca26fc5da88597ed1622e
    Signed-off-by: Martin Roth <martinroth at chromium.org>
    Original-Commit-Id: 9de93beae09174d50a31d2df655529f71628f77c
    Original-Change-Id: Ide23fff04fd63fb0afc538b610b7685756f79f8d
    Original-Signed-off-by: Lin Huang <hl at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/352953
    Original-Commit-Ready: Vadim Bendebury <vbendeb at chromium.org>
    Original-Tested-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-by: Douglas Anderson <dianders at chromium.org>
    Original-Reviewed-by: Derek Basehore <dbasehore at chromium.org>
    Reviewed-on: https://review.coreboot.org/15307
    Tested-by: build bot (Jenkins)
    Reviewed-by: Furquan Shaikh <furquan at google.com>


See https://review.coreboot.org/15307 for details.

-gerrit