[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake: Move PMC BAR setup to bootblock

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15332

-gerrit

commit f31bf662c2849e63bec22fb70d891b6c3e1202c0
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Wed Jun 22 18:58:14 2016 -0700

    soc/intel/apollolake: Move PMC BAR setup to bootblock
    
    Some features of PMC needs to be accessed before romstage. Hence,
    move PMC BARs setup into bootblock.
    
    BUG=chrome-os-partner:54149
    BRANCH=none
    TEST=none
    
    Change-Id: I14493498314ef1a4ce383e192edccf65fed2d2cb
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/bootblock/bootblock.c | 17 +++++++++++++++++
 src/soc/intel/apollolake/romstage.c            | 14 --------------
 2 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 431dd73..8413075 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -134,8 +134,25 @@ static void enable_spibar(void)
 	spi_init();
 }
 
+static void enable_pmcbar(void)
+{
+	device_t pmc = PMC_DEV;
+
+	/* Set PMC base addresses and enable decoding. */
+	pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0);
+	pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0);	/* 64-bit BAR */
+	pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1);
+	pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0);	/* 64-bit BAR */
+	pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
+	pci_write_config16(pmc, PCI_COMMAND,
+				PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+				PCI_COMMAND_MASTER);
+}
+
 void bootblock_soc_early_init(void)
 {
+	enable_pmcbar();
+
 	/* Prepare UART for serial console. */
 	if (IS_ENABLED(CONFIG_SOC_UART_DEBUG))
 		soc_console_uart_init();
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 0c8f1c2..ce28326 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -65,28 +65,14 @@ static struct chipset_power_state power_state CAR_GLOBAL;
 /*
  * Enables several BARs and devices which are needed for memory init
  * - MCH_BASE_ADDR is needed in order to talk to the memory controller
- * - PMC_BAR0 and PMC_BAR1 are used by FSP (with the base address hardcoded)
- *   Once raminit is done, we can safely let the allocator re-assign them
  * - HPET is enabled because FSP wants to store a pointer to global data in the
  *   HPET comparator register
  */
 static void soc_early_romstage_init(void)
 {
-	device_t pmc = PMC_DEV;
-
 	/* Set MCH base address and enable bit */
 	pci_write_config32(NB_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1);
 
-	/* Set PMC base addresses and enable decoding. */
-	pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0);
-	pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0);	/* 64-bit BAR */
-	pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1);
-	pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0);	/* 64-bit BAR */
-	pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
-	pci_write_config16(pmc, PCI_COMMAND,
-				PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
-				PCI_COMMAND_MASTER);
-
 	/* Enable decoding for HPET. Needed for FSP global pointer storage */
 	pci_write_config8(P2SB_DEV, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
 						P2SB_HPTC_ADDRESS_ENABLE);