[coreboot-gerrit] New patch to review for coreboot: armv7-r: add armv7-r configuration
hakim giydan (hgiydan@marvell.com)
gerrit at coreboot.org
Thu Jun 23 18:24:33 CEST 2016
hakim giydan (hgiydan at marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15335
-gerrit
commit 297ceac30d5373999b17be8e062ebd8b572c6b1d
Author: Hakim Giydan <hgiydan at marvell.com>
Date: Thu Jun 23 09:19:31 2016 -0700
armv7-r: add armv7-r configuration
this change adds armv7-r configuration for romstage and verstage
and any other files needed.
Change-Id: If94415d07fd6bd96c43d087374f609a2211f1885
Signed-off-by: Hakim Giydan <hgiydan at marvell.com>
---
src/arch/arm/armv7/Kconfig | 10 ++++
src/arch/arm/armv7/Makefile.inc | 27 ++++++++-
src/arch/arm/armv7/cache_r.c | 80 +++++++++++++++++++++++++++
src/arch/arm/armv7/cpu_r.S | 116 +++++++++++++++++++++++++++++++++++++++
src/arch/arm/armv7/exception_r.c | 37 +++++++++++++
util/xcompile/xcompile | 3 +-
6 files changed, 271 insertions(+), 2 deletions(-)
diff --git a/src/arch/arm/armv7/Kconfig b/src/arch/arm/armv7/Kconfig
index 0ab3542..26a7140 100644
--- a/src/arch/arm/armv7/Kconfig
+++ b/src/arch/arm/armv7/Kconfig
@@ -13,9 +13,19 @@ config ARCH_ROMSTAGE_ARMV7
config ARCH_RAMSTAGE_ARMV7
def_bool n
select ARCH_RAMSTAGE_ARM
+
config ARCH_BOOTBLOCK_ARMV7_M
def_bool n
select ARCH_BOOTBLOCK_ARM
+
config ARCH_VERSTAGE_ARMV7_M
def_bool n
select ARCH_VERSTAGE_ARM
+
+config ARCH_VERSTAGE_ARMV7_R
+ def_bool n
+ select ARCH_VERSTAGE_ARM
+
+config ARCH_ROMSTAGE_ARMV7_R
+ def_bool n
+ select ARCH_ROMSTAGE_ARM
diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc
index 2e9c49c..045e788 100644
--- a/src/arch/arm/armv7/Makefile.inc
+++ b/src/arch/arm/armv7/Makefile.inc
@@ -3,6 +3,7 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2013 The ChromiumOS Authors
+## Copyright (C) 2016 Marvell Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -18,9 +19,10 @@
armv7_flags = -mthumb -I$(src)/arch/arm/include/armv7/ -D__COREBOOT_ARM_ARCH__=7
armv7-a_flags = -march=armv7-a $(armv7_flags)
armv7-m_flags = -march=armv7-m $(armv7_flags)
+armv7-r_flags = -march=armv7-r $(armv7_flags)
armv7_asm_flags = -Wa,-mthumb -Wa,-mimplicit-it=always -Wa,-mno-warn-deprecated
-
+armv7-r_asm_flags = $(armv7-r_flags) $(armv7_asm_flags)
###############################################################################
# bootblock
###############################################################################
@@ -73,6 +75,17 @@ libverstage-S-ccopts += $(armv7_asm_flags)
verstage-generic-ccopts += $(armv7-m_flags)
verstage-S-ccopts += $(armv7_asm_flags)
+else ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV7_R),y)
+libverstage-generic-ccopts += $(armv7-r_flags)
+libverstage-S-ccopts += $(armv7-r_asm_flags)
+verstage-generic-ccopts += $(armv7-r_flags)
+verstage-S-ccopts += $(armv7-r_asm_flags)
+
+verstage-y += cache_r.c
+verstage-y += cpu_r.S
+verstage-y += exception_r.c
+verstage-y += mmu.c
+
endif # CONFIG_ARCH_VERSTAGE_ARMV7_M
################################################################################
@@ -91,6 +104,18 @@ romstage-S-ccopts += $(armv7_asm_flags)
rmodules_arm-generic-ccopts += $(armv7-a_flags)
rmodules_arm-S-ccopts += $(armv7_asm_flags)
+else ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7_R),y)
+romstage-y += cache_r.c
+romstage-y += cpu_r.S
+romstage-y += exception_r.c
+romstage-y += mmu.c
+
+romstage-generic-ccopts += $(armv7-r_flags)
+romstage-S-ccopts += $(armv7-r_asm_flags)
+
+rmodules_arm-generic-ccopts += $(armv7-r_flags)
+rmodules_arm-S-ccopts += $(armv7-r_asm_flags)
+
endif # CONFIG_ARCH_ROMSTAGE_ARMV7
###############################################################################
diff --git a/src/arch/arm/armv7/cache_r.c b/src/arch/arm/armv7/cache_r.c
new file mode 100644
index 0000000..341208f
--- /dev/null
+++ b/src/arch/arm/armv7/cache_r.c
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ * Copyright 2016 Marvell Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * cache.c: Cache maintenance routines for ARMv7-R
+ */
+
+#include <stdint.h>
+
+#include <arch/cache.h>
+
+void tlb_invalidate_all(void)
+{
+}
+
+void dcache_clean_all(void)
+{
+}
+
+void dcache_clean_invalidate_all(void)
+{
+}
+
+void dcache_invalidate_all(void)
+{
+}
+
+unsigned int dcache_line_bytes(void)
+{
+ return 0;
+}
+
+void dcache_clean_by_mva(void const *addr, size_t len)
+{
+}
+
+void dcache_clean_invalidate_by_mva(void const *addr, size_t len)
+{
+}
+
+void dcache_invalidate_by_mva(void const *addr, size_t len)
+{
+}
+
+void dcache_mmu_disable(void)
+{
+}
+
+void dcache_mmu_enable(void)
+{
+}
+
+void cache_sync_instructions(void)
+{
+}
diff --git a/src/arch/arm/armv7/cpu_r.S b/src/arch/arm/armv7/cpu_r.S
new file mode 100644
index 0000000..5c53def
--- /dev/null
+++ b/src/arch/arm/armv7/cpu_r.S
@@ -0,0 +1,116 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Marvell, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/asm.h>
+
+ENTRY(cpu_disable_dcache)
+
+ /* Read System Control Register configuration dat */
+ mrc p15, 0, R0, c1, c0, 0
+
+ bic R0, R0, #0x1 <<2
+ dsb
+
+ /* disable data cache */
+ mcr p15, 0, R0, c1, c0, 0
+
+ bx lr
+
+ENDPROC(cpu_disable_dcache)
+
+ENTRY(cpu_enable_dcache)
+
+ /* Read System Control Register configuration data */
+ mcr p15, 0, R1, c1, c0, 0
+
+ orr R1, R1, #0x1 <<2
+ mov R0, #0
+ dsb
+
+ /* Invalidate entire data cache */
+ mcr p15, 0, r0, c15, c5, 0
+
+ /* enabled data cache */
+ mcr p15, 0, R1, c1, c0, 0
+
+ bx lr
+
+ENDPROC(cpu_enable_dcache)
+
+ENTRY(cpu_disable_icache)
+
+ /* Read System Control Register configuration data */
+ mcr p15, 0, R0, c1, c0, 0
+
+ /* enable instruction cache */
+ bic R0, R0, #0x1 <<12
+
+ /* disable instruction cache */
+ mcr p15, 0, R0, c1, c0, 0
+
+ isb
+
+ bx lr
+
+ENDPROC(cpu_disable_icache)
+
+ENTRY(cpu_enable_icache)
+
+ /* Read System Control Register configuration data */
+ mrc p15, 0, R1, c1, c0, 0
+
+ /* enable instruction cache */
+ orr R1, R1, #0x1 <<12
+
+ mov R0, #0
+
+ /* Invalidate entire instruction cache */
+ mcr p15, 0, r0, c7, c5, 0
+
+ /* enable instruction cache */
+ mcr p15, 0, R1, c1, c0, 0
+
+ isb
+
+ bx lr
+
+ENDPROC(cpu_enable_icache)
+
+ENTRY(cpu_init)
+
+ mrc p15,0,r0,c9,c14,0
+ mov r0, $1
+ mcr p15,0,r0,c9,c14,0
+
+ /* read performance monitor control register into R0 */
+ mrc p15, 0, r0, c9, c12, 0
+
+ /* set the enable-bit for the performance counters and cycle counter */
+ orr r0, r0, #1
+
+ /* write the perfomance monitor control register back */
+ mcr p15, 0, r0, c9, c12, 0
+
+ /* load the bit-mask into r0 */
+ mov r0, #0x80000000
+
+ /* write the bit-mask to the enable set register
+ * and enable cycle counter bit
+ */
+ mcr p15, 0, r0, c9, c12, 1
+
+ bx lr
+
+ENDPROC(cpu_init)
diff --git a/src/arch/arm/armv7/exception_r.c b/src/arch/arm/armv7/exception_r.c
new file mode 100644
index 0000000..4bea53c
--- /dev/null
+++ b/src/arch/arm/armv7/exception_r.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ * Copyright 2016 Marvell Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <arch/exception.h>
+#include <console/console.h>
+
+void exception_init(void)
+{
+ printk(BIOS_DEBUG, "Exception handlers not installed.\n");
+}
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 13a0e8f..c030545 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -5,6 +5,7 @@
# Copyright (C) 2007-2010 coresystems GmbH
# Copyright (C) 2012 Google Inc
# Copyright (C) 2016 Raptor Engineering, LLC
+# Copyright (C) 2016 Marvell Inc
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -316,7 +317,7 @@ arch_config_arm() {
TBFDARCHS="littlearm"
TCLIST="armv7-a armv7a arm"
TWIDTH="32"
- TSUPP="arm armv4 armv7 armv7_m"
+ TSUPP="arm armv4 armv7 armv7_m armv7_r"
TABI="eabi"
}
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