[coreboot-gerrit] Patch set updated for coreboot: Revert "intel/apollolake: Use custom reset calls"

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15331

-gerrit

commit 3f5f3b68ca1ddc1c80d95d081c9f3dfce59205e8
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Thu Jun 23 08:26:00 2016 -0700

    Revert "intel/apollolake: Use custom reset calls"
    
    Looks like we need to do real cold reset in some FSP flows, so
    reverting this.
    
    This reverts commit 6f762171de4b8514fddd430052cbf24524e09e5d.
    
    Change-Id: Ie948d264c4e2572dab26fdb9462905247a168177
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/Kconfig      |  4 +--
 src/soc/intel/apollolake/Makefile.inc |  3 ---
 src/soc/intel/apollolake/reset.c      | 50 -----------------------------------
 3 files changed, 1 insertion(+), 56 deletions(-)

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index d830a9f..98ce7d8 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -59,11 +59,9 @@ config TPM_ON_FAST_SPI
 	 TPM part is conntected on Fast SPI interface, but the LPC MMIO
 	 TPM transactions are decoded and serialized over the SPI interface.
 
-# TODO(furquan): Use common reset once USB LDO issue is resolved in future
-# steppings.
 config SOC_INTEL_COMMON_RESET
 	bool
-	default n
+	default y
 
 config MMCONF_BASE_ADDRESS
 	hex "PCI MMIO Base Address"
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 7d49b06..4ad6f0f 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -29,7 +29,6 @@ romstage-y += meminit.c
 romstage-y += mmap_boot.c
 romstage-y += tsc_freq.c
 romstage-y += pmutil.c
-romstage-y += reset.c
 romstage-y += spi.c
 
 smm-y += mmap_boot.c
@@ -57,7 +56,6 @@ ramstage-y += pmutil.c
 ramstage-y += pmc.c
 ramstage-y += smi.c
 ramstage-y += spi.c
-ramstage-y += reset.c
 
 postcar-y += exit_car.S
 postcar-y += memmap.c
@@ -72,7 +70,6 @@ verstage-y += mmap_boot.c
 verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 verstage-y += tsc_freq.c
 verstage-y += pmutil.c
-verstage-y += reset.c
 verstage-y += spi.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c
deleted file mode 100644
index eb43c41..0000000
--- a/src/soc/intel/apollolake/reset.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2014-2016 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/hlt.h>
-#include <arch/io.h>
-#include <halt.h>
-#include <reset.h>
-
-/* Reset control port */
-#define RST_CNT			0xcf9
-#define FULL_RST		(1 << 3)
-#define RST_CPU			(1 << 2)
-#define SYS_RST			(1 << 1)
-
-/*
- * Temporary disable cold reboot on Apollolake platform due to USB LDO issue.
- * Should be fixed in later stepping.
- */
-void hard_reset(void)
-{
-	soft_reset();
-}
-
-void soft_reset(void)
-{
-	/* PMC_PLTRST# asserted. */
-	outb(RST_CPU | SYS_RST, RST_CNT);
-	halt();
-}
-
-void cpu_reset(void)
-{
-	/* Sends INIT# to CPU */
-	outb(RST_CPU, RST_CNT);
-	halt();
-}