[coreboot-gerrit] New patch to review for coreboot: WIP: soc/intel/apollolake: Change default CAR size to 768 KiB

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15453

-gerrit

commit d1fb0de07a0d573cd9c251304ef4ba2d47d741a3
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Mon Jun 27 13:37:51 2016 -0700

    WIP: soc/intel/apollolake: Change default CAR size to 768 KiB
    
    As whole 1024 KiB is not used, it is possible to shrink CAR size
    to 768 KiB. Since 768 KiB is not power of two, 2 MTRRs are used
    to setup it. This is part of preparation for CQOS enabling.
    
    BUG=chrome-os-partner:51959
    
    Change-Id: I56326a1790df202a0e428e092dd90286c58763c5
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/Kconfig                  | 26 ++++++++++++-
 src/soc/intel/apollolake/bootblock/cache_as_ram.S | 46 +++++++++++++++++++++++
 2 files changed, 71 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 98ce7d8..fd4e5ac 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -77,7 +77,7 @@ config DCACHE_RAM_BASE
 
 config DCACHE_RAM_SIZE
 	hex "Length in bytes of cache-as-RAM"
-	default 0x100000
+	default 0xc0000
 	help
 	  The size of the cache-as-ram region required during bootblock
 	  and/or romstage.
@@ -182,4 +182,28 @@ config IFWI_FILE_NAME
 	help
 	  Name of file to store in the IFWI region.
 
+choice
+	prompt "Cache-as-ram implementation"
+	default CAR_CQOS
+	help
+	  This option allows you to select how cache-as-ram (CAR) is set up.
+
+config CAR_NEM
+	bool "Non-evict mode"
+	help
+	  Traditionally, CAR is set up by using Non-Evict mode. This method
+	  does not allow CAR and cache to co-exist, because cache fills are
+	  block in NEM mode.
+
+
+config CAR_CQOS
+	bool "Cache Quality of Service"
+	help
+	  Cache Quality of Service allows more fine-grained control of cache
+	  usage. As result, it is possible to set up portion of L2 cache for
+	  CAR and use remainded for actual caching.
+
+endchoice
+
+
 endif
diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S
index 8647206..3c97bb2 100644
--- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S
+++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S
@@ -70,6 +70,31 @@ clear_var_mtrr:
 
 	post_code(0x24)
 
+#if (CONFIG_DCACHE_RAM_SIZE == 0xc0000) /* 768 KiB */
+	/* 512 KiB */
+	mov	$MTRR_PHYS_BASE(0), %ecx
+	mov	$CONFIG_DCACHE_RAM_BASE, %eax
+	or	$MTRR_TYPE_WRBACK, %eax
+	xor	%edx,%edx
+	wrmsr
+
+	mov	$MTRR_PHYS_MASK(0), %ecx
+	mov	$~(0x80000 - 1), %eax	/* size mask */
+	or	$MTRR_PHYS_MASK_VALID, %eax
+	wrmsr
+
+	/* 256 KiB */
+	mov	$MTRR_PHYS_BASE(1), %ecx
+	mov	$(CONFIG_DCACHE_RAM_BASE + 0x80000), %eax
+	or	$MTRR_TYPE_WRBACK, %eax
+	xor	%edx,%edx
+	wrmsr
+
+	mov	$MTRR_PHYS_MASK(1), %ecx
+	mov	$~(0x40000 - 1), %eax	/* size mask */
+	or	$MTRR_PHYS_MASK_VALID, %eax
+	wrmsr
+#else
 	/* Configure CAR region as write-back (WB) */
 	mov	$MTRR_PHYS_BASE(0), %ecx
 	mov	$CONFIG_DCACHE_RAM_BASE, %eax
@@ -82,6 +107,7 @@ clear_var_mtrr:
 	mov	$~(CONFIG_DCACHE_RAM_SIZE - 1), %eax	/* size mask */
 	or	$MTRR_PHYS_MASK_VALID, %eax
 	wrmsr
+#endif
 
 	post_code(0x25)
 
@@ -97,12 +123,30 @@ clear_var_mtrr:
 	invd
 	mov	%eax, %cr0
 
+#if IS_ENABLED(CONFIG_CAR_NEM)
 	/* Disable cache eviction (setup stage) */
 	mov	$MSR_EVICT_CTL, %ecx
 	rdmsr
 	or	$0x1, %eax
 	wrmsr
+#endif
 
+#if IS_ENABLED(CONFIG_CAR_CQOS)
+	/* Mask 0 is used for CAR */
+	mov     $MTRR_L2_QOS_MASK(0), %ecx
+	rdmsr
+	/* Calculate how many bits to be used for CAR */
+	mov     $(1 << (CONFIG_DCACHE_RAM_SIZE / CACHE_QOS_SIZE_PER_BIT) - 1), %al
+	wrmsr
+
+	/* Mask 1 is used for evicatable cache */
+	mov     $MTRR_L2_QOS_MASK(1), %ecx
+	rdmsr
+	/* Invert bits that are to be used for cache */
+	mov     $(1 << (CONFIG_DCACHE_RAM_SIZE / CACHE_QOS_SIZE_PER_BIT) - 1), %al
+	xor     $~0, %al
+	wrmsr
+#endif
 	post_code(0x26)
 
 	/* Clear the cache memory region. This will also fill up the cache */
@@ -113,11 +157,13 @@ clear_var_mtrr:
 
 	post_code(0x27)
 
+#if IS_ENABLED(CONFIG_CAR_NEM)
 	/* Disable cache eviction (run stage) */
 	mov	$MSR_EVICT_CTL, %ecx
 	rdmsr
 	or	$0x2, %eax
 	wrmsr
+#endif
 
 	post_code(0x28)