[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake: Remove UPDs that are no longer valid

[Brandon Breitenstein (brandon.breitenstein@intel.com)]

Brandon Breitenstein (brandon.breitenstein at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15458

-gerrit

commit abe74ce8ab28998bd93d5f25b925b337808d0587
Author: Brandon Breitenstein <brandon.breitenstein at intel.com>
Date:   Fri Jun 24 12:09:50 2016 -0700

    soc/intel/apollolake: Remove UPDs that are no longer valid
    
    Removing base address upds that are no longer valid from coreboot
    This is required for use with the FSP 143_10 header files.
    
    BUG=chrome-os-partner:54677
    BRANCH=none
    TEST=built image with FSP 143_10 headers
    
    Change-Id: Id34c6a397d7de432c2450a7617d28b57bfe0d804
    Signed-off-by: Brandon Breitenstein <brandon.breitenstein at intel.com>
---
 src/soc/intel/apollolake/chip.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 821570b..044ef91 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -253,12 +253,6 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
 	if (cfg->emmc_rx_cmd_data_cntl2 != 0)
 		silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2;
 
-	/* Our defaults may not match FSP defaults, so set them explicitly */
-	silconfig->AcpiBase = ACPI_PMIO_BASE;
-	/* First 4k in BAR0 is used for IPC, real registers start at 4k offset */
-	silconfig->PmcBase = PMC_BAR0 + 0x1000;
-	silconfig->P2sbBase = P2SB_BAR;
-
 	silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
 
 	/* Disable setting of EISS bit in FSP. */