[coreboot-gerrit] Patch set updated for coreboot: WIP: soc/intel/apollolake: Cache cbmem region

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15456

-gerrit

commit 02dd47ce7f3d1673403f99499127be2ebd0e4b3a
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Fri Jun 24 18:40:28 2016 -0700

    WIP: soc/intel/apollolake: Cache cbmem region
    
    Configure write-back MTRRs so that 16 MiB under cbmem_top is cached.
    This allows caching of FSP reserved memory and postcar stage itself.
    On CAR teardown the memory is flushed with clflush instruction.
    Depending on what cache configuration is used, either L1 (NEM) or
    both L1 and L2 (CQOS) storage is used for caching purposes.
    
    This is WIP patch, because currently location of cbmem_top can not
    be known before memory is trained. So addresses are hardcoded.
    
    BUG=chrome-os-partner:51959
    TEST=run primitive memtest on 16 MiB cached memory region after mem
    is trained, observe x7 improvement on L1 only, x12 on L2 of 256 KiB
    
    Change-Id: I62aad238a3056f9bbe5327dfb33a2a1112d61194
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/exit_car.S | 8 ++++++++
 src/soc/intel/apollolake/romstage.c | 9 ++++++++-
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/exit_car.S b/src/soc/intel/apollolake/exit_car.S
index e5706cf..c0fb39b 100644
--- a/src/soc/intel/apollolake/exit_car.S
+++ b/src/soc/intel/apollolake/exit_car.S
@@ -38,6 +38,14 @@ chipset_teardown_car:
 	and	$(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax
 	wrmsr
 
+	/* Flush down whatever we have */
+	mov	$0x7a000000, %eax
+loop:
+	clflush	(%eax)
+	add	$CACHE_LINE_SIZE, %eax
+	cmp	$0x7b000000, %eax
+	jl	loop
+
 #if IS_ENABLED(CONFIG_CAR_CQOS)
 	mov	$MTRR_L2_QOS_MASK(0), %ecx
 	rdmsr
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index ce28326..1fa52fd 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -112,7 +112,7 @@ asmlinkage void car_stage_entry(void)
 	struct postcar_frame pcf;
 	size_t  mrc_data_size;
 	uintptr_t top_of_ram;
-	int prev_sleep_state;
+	int prev_sleep_state, mtrr;
 	struct romstage_handoff *handoff;
 	struct chipset_power_state *ps = car_get_var_ptr(&power_state);
 
@@ -129,6 +129,13 @@ asmlinkage void car_stage_entry(void)
 	range_entry_init(&reg_car, (uintptr_t)_car_relocatable_data_end,
 			(uintptr_t)_car_region_end, 0);
 
+	mtrr = get_free_var_mtrr();
+	if (mtrr==-1)
+		printk(BIOS_CRIT, "no available MTRRs to cache cbmem!\n");
+	else
+		/* Make sure cbmem 16 MiB under CBMEM is cachable */
+		set_var_mtrr(mtrr, 0x7a000000, 16 * MiB, MTRR_TYPE_WRBACK);
+
 	if (fsp_memory_init(&hob_list_ptr, &reg_car) != FSP_SUCCESS) {
 		die("FSP memory init failed. Giving up.");
 	}