[coreboot-gerrit] Patch set updated for coreboot: intel post-car: Consolidate choose_top_of_stack()
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Tue Jun 28 10:17:08 CEST 2016
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15463
-gerrit
commit da85ad95f13f3a15dcc2c9a2cce35be85a72b2d6
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Mon Jun 27 14:50:27 2016 +0300
intel post-car: Consolidate choose_top_of_stack()
Change-Id: I2c49d68ea9a8f52737b6064bc4fa703bdb1af1df
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/Kconfig | 4 +++
src/cpu/intel/haswell/romstage.c | 16 +----------
src/drivers/intel/fsp1_1/Kconfig | 4 ---
src/drivers/intel/fsp1_1/stack.c | 20 ++------------
src/include/program_loading.h | 5 ++++
src/lib/Makefile.inc | 1 +
src/lib/romstage_stack.c | 44 ++++++++++++++++++++++++++++++
src/soc/intel/baytrail/romstage/romstage.c | 16 +----------
src/soc/intel/broadwell/romstage/stack.c | 17 ++----------
9 files changed, 60 insertions(+), 67 deletions(-)
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index a026b28..37d6513 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -25,6 +25,10 @@ config DCACHE_BSP_STACK_SLUSH
config DCACHE_AP_STACK_SIZE
hex
+config ROMSTAGE_RAM_STACK_SIZE
+ hex "Size of the romstage RAM stack in bytes"
+ default 0x5000
+
config SMP
bool
default y if MAX_CPUS != 1
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index cde9441..8354aeb 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -65,20 +65,6 @@ static inline u32 *stack_push(u32 *stack, u32 value)
return stack;
}
-/* Romstage needs quite a bit of stack for decompressing images since the lzma
- * lib keeps its state on the stack during romstage. */
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-static unsigned long choose_top_of_stack(void)
-{
- unsigned long stack_top;
-
- /* cbmem_add() does a find() before add(). */
- stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
- ROMSTAGE_RAM_STACK_SIZE);
- stack_top += ROMSTAGE_RAM_STACK_SIZE;
- return stack_top;
-}
-
/* setup_romstage_stack_after_car() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */
static void *setup_romstage_stack_after_car(void)
@@ -90,7 +76,7 @@ static void *setup_romstage_stack_after_car(void)
u32 top_of_ram;
/* Top of stack needs to be aligned to a 4-byte boundary. */
- top_of_stack = choose_top_of_stack() & ~3;
+ top_of_stack = romstage_ram_stack() & ~3;
slot = (void *)top_of_stack;
num_mtrrs = 0;
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index 86f6c7b..59b4797 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -99,10 +99,6 @@ config GOP_SUPPORT
bool "Enable GOP support"
default n
-config ROMSTAGE_RAM_STACK_SIZE
- hex "Size of the romstage RAM stack in bytes"
- default 0x5000
-
config USE_GENERIC_FSP_CAR_INC
bool
default n
diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c
index 65ba235..b0e4992 100644
--- a/src/drivers/intel/fsp1_1/stack.c
+++ b/src/drivers/intel/fsp1_1/stack.c
@@ -21,23 +21,7 @@
#include <fsp/romstage.h>
#include <fsp/stack.h>
#include <stdlib.h>
-
-const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE;
-
-/*
- * Romstage needs quite a bit of stack for decompressing images since the lzma
- * lib keeps its state on the stack during romstage.
- */
-static unsigned long choose_top_of_stack(void)
-{
- unsigned long stack_top;
-
- /* cbmem_add() does a find() before add(). */
- stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
- romstage_ram_stack_size);
- stack_top += romstage_ram_stack_size;
- return stack_top;
-}
+#include <program_loading.h>
/*
* setup_stack_and_mtrrs() determines the stack to use after
@@ -57,7 +41,7 @@ void *setup_stack_and_mtrrs(void)
soc_display_mtrrs();
/* Top of stack needs to be aligned to a 8-byte boundary. */
- top_of_stack = choose_top_of_stack();
+ top_of_stack = romstage_ram_stack();
slot = (void *)top_of_stack;
num_mtrrs = 0;
max_mtrrs = soc_get_variable_mtrr_count(NULL);
diff --git a/src/include/program_loading.h b/src/include/program_loading.h
index 42addb8..929d60c 100644
--- a/src/include/program_loading.h
+++ b/src/include/program_loading.h
@@ -170,6 +170,11 @@ void run_ramstage(void);
/* Called when the stage cache couldn't load ramstage on resume. */
void ramstage_cache_invalid(void);
+/* Determine where stack for ramstage loader is located. */
+unsigned long romstage_ram_stack_maybe_low(int no_cbmem);
+unsigned long romstage_ram_stack(void);
+extern const unsigned long romstage_ram_stack_size;
+
/***********************
* PAYLOAD LOADING *
***********************/
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 1028917..0c34b75 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -78,6 +78,7 @@ romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c
ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c
romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c
romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
+romstage-y += romstage_stack.c
romstage-y += stack.c
ramstage-y += rtc.c
diff --git a/src/lib/romstage_stack.c b/src/lib/romstage_stack.c
new file mode 100644
index 0000000..319d354
--- /dev/null
+++ b/src/lib/romstage_stack.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <program_loading.h>
+#include <cbmem.h>
+
+const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE;
+
+/*
+ * Romstage needs quite a bit of stack for decompressing images since the lzma
+ * lib keeps its state on the stack during romstage.
+ */
+unsigned long romstage_ram_stack_maybe_low(int no_cbmem)
+{
+ unsigned long stack_top;
+
+ if (no_cbmem)
+ return CONFIG_RAMTOP;
+
+ /* cbmem_add() does a find() before add(). */
+ stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
+ romstage_ram_stack_size);
+ stack_top += romstage_ram_stack_size;
+ return stack_top;
+}
+
+unsigned long romstage_ram_stack(void)
+{
+ int no_cbmem = IS_ENABLED(CONFIG_LATE_CBMEM_INIT);
+ return romstage_ram_stack_maybe_low(no_cbmem);
+}
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index a167c90..6cf13bc 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -258,20 +258,6 @@ static inline uint32_t *stack_push(u32 *stack, u32 value)
return stack;
}
-/* Romstage needs quite a bit of stack for decompressing images since the lzma
- * lib keeps its state on the stack during romstage. */
-static unsigned long choose_top_of_stack(void)
-{
- unsigned long stack_top;
- const unsigned long romstage_ram_stack_size = 0x5000;
-
- /* cbmem_add() does a find() before add(). */
- stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
- romstage_ram_stack_size);
- stack_top += romstage_ram_stack_size;
- return stack_top;
-}
-
/* setup_stack_and_mttrs() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */
static void *setup_stack_and_mttrs(void)
@@ -283,7 +269,7 @@ static void *setup_stack_and_mttrs(void)
uint32_t top_of_ram;
/* Top of stack needs to be aligned to a 4-byte boundary. */
- top_of_stack = choose_top_of_stack() & ~3;
+ top_of_stack = romstage_ram_stack() & ~3;
slot = (void *)top_of_stack;
num_mtrrs = 0;
diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c
index 6c602a8..87f56ad 100644
--- a/src/soc/intel/broadwell/romstage/stack.c
+++ b/src/soc/intel/broadwell/romstage/stack.c
@@ -21,6 +21,7 @@
#include <cbmem.h>
#include <cpu/x86/mtrr.h>
#include <soc/romstage.h>
+#include <program_loading.h>
static inline uint32_t *stack_push(u32 *stack, u32 value)
{
@@ -29,20 +30,6 @@ static inline uint32_t *stack_push(u32 *stack, u32 value)
return stack;
}
-/* Romstage needs quite a bit of stack for decompressing images since the lzma
- * lib keeps its state on the stack during romstage. */
-static unsigned long choose_top_of_stack(void)
-{
- unsigned long stack_top;
- const unsigned long romstage_ram_stack_size = 0x5000;
-
- /* cbmem_add() does a find() before add(). */
- stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
- romstage_ram_stack_size);
- stack_top += romstage_ram_stack_size;
- return stack_top;
-}
-
/* setup_stack_and_mttrs() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */
void *setup_stack_and_mttrs(void)
@@ -54,7 +41,7 @@ void *setup_stack_and_mttrs(void)
uint32_t top_of_ram;
/* Top of stack needs to be aligned to a 4-byte boundary. */
- top_of_stack = choose_top_of_stack() & ~3;
+ top_of_stack = romstage_ram_stack() & ~3;
slot = (void *)top_of_stack;
num_mtrrs = 0;
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