[coreboot-gerrit] New patch to review for coreboot: AGESA: Use common romstage ram stack

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15466

-gerrit

commit 23e293f2ea14dea275097dde7bf225aecb2e03d9
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Mon Jun 27 16:15:02 2016 +0300

    AGESA: Use common romstage ram stack
    
    Change-Id: Ie120360fa79aa0f6f6d82606838404bb0b0d9681
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/arch/x86/acpi_s3.c             | 3 +++
 src/cpu/amd/agesa/Kconfig          | 4 ++++
 src/cpu/amd/agesa/s3_resume.c      | 3 ++-
 src/cpu/amd/agesa/s3_resume.h      | 4 ++++
 src/lib/Makefile.inc               | 1 +
 src/northbridge/amd/agesa/oem_s3.c | 3 ---
 6 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c
index 7855a2f..bb52313 100644
--- a/src/arch/x86/acpi_s3.c
+++ b/src/arch/x86/acpi_s3.c
@@ -19,6 +19,7 @@
 #include <cbmem.h>
 #include <cpu/cpu.h>
 #include <timestamp.h>
+#include <program_loading.h>
 #include <romstage_handoff.h>
 #include <rules.h>
 
@@ -100,6 +101,8 @@ void acpi_prepare_resume_backup(void)
 	 * it being there during reboot time. We don't need the pointer, nor
 	 * the result right now. If it fails, ACPI resume will be disabled.
 	 */
+	if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT))
+		romstage_ram_stack_maybe_low(0);
 
 	if (HIGH_MEMORY_SAVE)
 		cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE);
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index ae5e854..e41b2c9 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -69,6 +69,10 @@ config S3_DATA_SIZE
 	int
 	default 32768
 
+config ROMSTAGE_RAM_STACK_SIZE
+	hex "Size of the romstage RAM stack in bytes"
+	default 0x18000
+
 endif # CPU_AMD_AGESA
 
 source src/cpu/amd/agesa/family10/Kconfig
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 54e41c1..f74374a 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -21,13 +21,14 @@
 #include <cpu/amd/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cbmem.h>
+#include <program_loading.h>
 #include <string.h>
 #include <halt.h>
 #include "s3_resume.h"
 
 static void move_stack_high_mem(void)
 {
-	void *high_stack = cbmem_find(CBMEM_ID_ROMSTAGE_RAM_STACK);
+	void *high_stack = (void*)romstage_ram_stack_maybe_low(0);
 	if (high_stack == NULL)
 		halt();
 
diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h
index ff23966..f47c8ba 100644
--- a/src/cpu/amd/agesa/s3_resume.h
+++ b/src/cpu/amd/agesa/s3_resume.h
@@ -38,4 +38,8 @@ void ResumeHeap(void **heap, size_t *len);
 
 #define HIGH_MEMORY_SCRATCH		0x30000
 
+#if (CONFIG_ROMSTAGE_RAM_STACK_SIZE < HIGH_ROMSTAGE_STACK_SIZE)
+#error
+#endif
+
 #endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 0c34b75..9012321 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -79,6 +79,7 @@ ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c
 romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c
 romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
 romstage-y += romstage_stack.c
+ramstage-y += romstage_stack.c
 romstage-y += stack.c
 ramstage-y += rtc.c
 
diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c
index 8cce0e7..da78c31 100644
--- a/src/northbridge/amd/agesa/oem_s3.c
+++ b/src/northbridge/amd/agesa/oem_s3.c
@@ -119,9 +119,6 @@ AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams)
 	u32 MTRRStorageSize = 0;
 	uintptr_t pos, size;
 
-	if (HIGH_ROMSTAGE_STACK_SIZE)
-		cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE);
-
 	/* To be consumed in AmdInitResume. */
 	get_s3nv_data(S3DataTypeNonVolatile, &pos, &size);
 	if (size && dataBlock->NvStorageSize)