[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Add NHLT table region to ACPI global nvs

Aaron Durbin (adurbin@chromium.org) gerrit at coreboot.org
Tue Jun 28 18:01:13 CEST 2016


Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15025

-gerrit

commit 17c086293f98c4f640ebef004a95e9d04a1595dd
Author: Saurabh Satija <saurabh.satija at intel.com>
Date:   Thu Mar 31 15:41:30 2016 -0700

    soc/intel/apollolake: Add NHLT table region to ACPI global nvs
    
    Add address and length of NHLT table in ACPI.
    
    Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a
    Signed-off-by: Saurabh Satija <saurabh.satija at intel.com>
---
 src/soc/intel/apollolake/acpi/globalnvs.asl | 2 ++
 src/soc/intel/apollolake/include/soc/nvs.h  | 4 +++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index b2b7f53..404f36c 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -36,6 +36,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	CBMC,	32,     // 0x05 - 0x08 - Coreboot Memory Console
 	PM1I,	64,     // 0x09 - 0x10 - System Wake Source - PM1 Index
 	GPEI,	64,     // 0x11 - 0x18 - GPE Wake Source
+	NHLA,	64,     // 0x19 - 0x20 - NHLT Address
+	NHLL,	32,     // 0x21 - 0x24 - NHLT Length
 
 	/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
 	Offset (0x100),
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index c791812..3e4f432 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -36,7 +36,9 @@ struct global_nvs_t {
 	uint32_t	cbmc; /* 0x05 - 0x08 - Coreboot Memory Console */
 	uint64_t	pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
 	uint64_t	gpei; /* 0x11 - 0x18 - GPE Wake Source */
-	uint8_t		unused[231];
+	uint64_t	nhla; /* 0x19 - 0x20 - NHLT Address */
+	uint32_t	nhll; /* 0x21 - 0x24 - NHLT Length */
+	uint8_t		unused[219];
 
 	/* ChromeOS specific (0x100 - 0xfff) */
 	chromeos_acpi_t chromeos;



More information about the coreboot-gerrit mailing list