[coreboot-gerrit] New patch to review for coreboot: ga-g41m-es2l: add cmos.layout

Arthur Heymans (arthur@aheymans.xyz) gerrit at coreboot.org
Tue Jun 28 23:15:35 CEST 2016


Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15493

-gerrit

commit a81768ecee815cd9c764951571a27b75e6f1f44d
Author: Arthur Heymans <arthur at aheymans.xyz>
Date:   Sat Jun 18 23:26:46 2016 +0200

    ga-g41m-es2l: add cmos.layout
    
    This adds a cmos.layout and a cmos.default to ga-g41m-es2l.
    This allows to set things like baud_rate, debug_level, etc.
    from cmos.
    
    Change-Id: I25df7a1f3a0ce486b96cfe05bda628f604b0baec
    Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
 src/mainboard/gigabyte/ga-g41m-es2l/Kconfig      |   2 +
 src/mainboard/gigabyte/ga-g41m-es2l/cmos.default |   5 +
 src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout  | 119 +++++++++++++++++++++++
 3 files changed, 126 insertions(+)

diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
index 7dec921..6452f4d 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
@@ -30,6 +30,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select PCIEXP_CLK_PM
 	select PCIEXP_L1_SUB_STATE
 	select REALTEK_8168_RESET
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
 
 config MMCONF_BASE_ADDRESS
 	hex
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
new file mode 100644
index 0000000..c20ba94
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
@@ -0,0 +1,5 @@
+boot_option=Fallback
+baud_rate=115200
+debug_level=Spew
+power_on_after_fail=Enable
+nmi=Enable
\ No newline at end of file
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout
new file mode 100644
index 0000000..f92de11
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout
@@ -0,0 +1,119 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+
+# coreboot config options: cpu
+#424          1       e       2        hyper_threading
+#425        7       r       0        unused
+
+# coreboot config options: northbridge
+432         4        e      11        gfx_uma_size
+#435        549       r       0        unused
+
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+11    0     1M
+11    1     4M
+11    2     8M
+11    3     16M
+11    4     32M
+11    5     48M
+11    6     64M
+11    7     128M
+11    8     256M
+11    9     96M
+11    10     160M
+11    11     224M
+11    12     352M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984



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