[coreboot-gerrit] Patch set updated for coreboot: fsp_broadwell_de: Enable Super I/O address range decode

[Werner Zeh (werner.zeh@siemens.com)]

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15495

-gerrit

commit 5c55ff11f7a742b4ed6ec8dc6b876a5ee38a3e71
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Wed Jun 29 07:17:21 2016 +0200

    fsp_broadwell_de: Enable Super I/O address range decode
    
    If there is an external 16550 like UART, one needs to enable
    the appropriate address ranges before console_init() is called
    so that the init sequence can reach the external UART. Otherwise
    the UART will only start working in ramstage and will produce
    unreadable characters in romstage due to the lack of initialization.
    
    Tested-on: Siemens MC_BDX1
    
    Change-Id: Iafc5b5b6df14916c5ed778928521d4a8f539cf46
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/soc/intel/fsp_broadwell_de/include/soc/lpc.h   | 4 +++-
 src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 3 +++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h
index 2c02ebd..0408f7f 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h
@@ -21,6 +21,8 @@
 #define REVID			0x08
 #define PIRQ_RCR1		0x60
 #define PIRQ_RCR2		0x68
+#define LPC_IO_DEC		0x80
+#define LPC_EN			0x82
 #define GEN_PMCON_1		0xA0
 #define GEN_PMCON_2		0xA2
 #define GEN_PMCON_3		0xA4
@@ -83,4 +85,4 @@
 #define   TCO_TMR_HALT		(1 << 11)
 #define TCO_TMR			0x70
 
-#endif /* _SOC_LPC_H_ */
\ No newline at end of file
+#endif /* _SOC_LPC_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index dc883a4..bdfcbc8 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -48,6 +48,9 @@ static void init_rtc(void)
 void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
 {
 	post_code(0x40);
+	/* Enable decoding of I/O locations for Super I/O devices */
+	pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_IO_DEC, 0x0010);
+	pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_EN, 0x340f);
 	console_init();
 	init_rtc();