[coreboot-gerrit] Patch merged into coreboot/master: nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 9f3f9154c9f3dd1e3cfbd2703b681c3e9ddf4dc7
Author: Patrick Rudolph <siro at das-labor.org>
Date:   Tue Jan 26 20:02:14 2016 +0100

    nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk
    
    Instead of hardcoding the maximum supported DDR frequency to
    800Mhz (DDR3-1600), read the fuse bits that encode this information.
    
    Test system:
     * Intel IvyBridge
     * Gigabyte GA-B75M-D3H
    
    Change-Id: I515a2695a490f16aeb946bfaf3a1e860c607cba9
    Signed-off-by: Patrick Rudolph <siro at das-labor.org>
    Reviewed-on: https://review.coreboot.org/13487
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/13487 for details.

-gerrit