[coreboot-gerrit] Patch set updated for coreboot: arch/x86: Add common assembly code for stages that run in CAR

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13861

-gerrit

commit c9149b0968f7d24877bad57b235f5bce26b469e2
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Sun Feb 28 22:37:15 2016 -0800

    arch/x86: Add common assembly code for stages that run in CAR
    
    This adds a few assembly lines that are generic enough to be shared
    between romstage and verstage that are ran in CAR. The GDT reload
    is bypassed and the stack is reloaded with the CAR stack defined
    in car.ld. The entry point for all those stages is car_stage_entry().
    
    Change-Id: Ie7ef6a02f62627f29a109126d08c68176075bd67
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/arch/x86/assembly_entry.S   | 31 ++++++++++++++++++++++++++++++-
 src/arch/x86/include/arch/cpu.h |  9 +++++++++
 2 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index 01e91b0..8f4d7c9 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -1,7 +1,8 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2015 Google Inc.
+ * Copyright 2016 Google Inc.
+ * Copyright (C) 2016 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -13,6 +14,8 @@
  * GNU General Public License for more details.
  */
 
+#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+
 /* This file assembles the start of the romstage program by the order of the
  * includes. Thus, it's extremely important that one pays very careful
  * attention to the order of the includes. */
@@ -31,3 +34,29 @@
  * cache-as-ram setup files would be here.
  */
 #include <generated/assembly.inc>
+
+#else
+
+.section ".text._start", "ax", @progbits
+.global _start
+_start:
+
+	/* reset stack pointer to CAR stack */
+	mov	$_car_stack_end, %esp
+
+	/* clear CAR_GLOBAL area as it is not shared */
+	cld
+	xor	%eax, %eax
+	movl	$(_car_global_end), %ecx
+	movl	$(_car_global_start), %edi
+	sub	%edi, %ecx
+	rep	stosl
+
+	jmp	car_stage_entry
+
+/* This is here for linking purposes. */
+.weak car_stage_entry
+car_stage_entry:
+1:
+	jmp	1b
+#endif
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 408fa15..f50901f 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -239,4 +239,13 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
 #define asmlinkage __attribute__((regparm(0)))
 #define alwaysinline inline __attribute__((always_inline))
 
+#ifndef __ROMCC__
+/*
+ * When using CONFIG_C_ENVIRONMENT_BOOTBLOCK the car_stage_entry()
+ * is the symbol jumped to for each stage after bootblock using
+ * cache-as-ram.
+ */
+void asmlinkage car_stage_entry(void);
+#endif
+
 #endif /* ARCH_CPU_H */