[coreboot-gerrit] Patch set updated for coreboot: rockchip: rk3399: support gpio

[Lin Huang (hl@rock-chips.com)]

Lin Huang (hl at rock-chips.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13919

-gerrit

commit 9f4f16cb219bcffbe3cb29e1960aac519a2ad0fe
Author: huang lin <hl at rock-chips.com>
Date:   Wed Mar 2 17:29:01 2016 +0800

    rockchip: rk3399: support gpio
    
    Change-Id: I1d213a91ea508997b876441250743671204d7c53
    Signed-off-by: huang lin <hl at rock-chips.com>
---
 src/soc/rockchip/rk3399/Makefile.inc       |  5 ++
 src/soc/rockchip/rk3399/gpio.c             | 78 ++++++++++++++++++++++++++++++
 src/soc/rockchip/rk3399/include/soc/gpio.h | 66 +++++++++++++++++++++++++
 3 files changed, 149 insertions(+)

diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc
index e9093ba..47dc1b8 100644
--- a/src/soc/rockchip/rk3399/Makefile.inc
+++ b/src/soc/rockchip/rk3399/Makefile.inc
@@ -22,6 +22,7 @@ bootblock-y += spi.c
 bootblock-y += clock.c
 bootblock-y += mmu_operations.c
 bootblock-y += i2c.c
+bootblock-y += gpio.c
 ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
 bootblock-$(CONFIG_DRIVERS_UART) += uart.c
 endif
@@ -32,6 +33,7 @@ verstage-y += timer.c
 verstage-y += spi.c
 verstage-y += clock.c
 verstage-y += i2c.c
+verstage-y += gpio.c
 
 ################################################################################
 
@@ -42,6 +44,8 @@ romstage-y += spi.c
 romstage-y += clock.c
 romstage-y += mmu_operations.c
 romstage-y += i2c.c
+romstage-y += gpio.c
+
 ################################################################################
 
 ramstage-y += cbmem.c
@@ -51,6 +55,7 @@ ramstage-y += timer.c
 ramstage-y += spi.c
 ramstage-y += clock.c
 ramstage-y += i2c.c
+ramstage-y += gpio.c
 
 ################################################################################
 
diff --git a/src/soc/rockchip/rk3399/gpio.c b/src/soc/rockchip/rk3399/gpio.c
new file mode 100644
index 0000000..0fa5ee4
--- /dev/null
+++ b/src/soc/rockchip/rk3399/gpio.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <gpio.h>
+#include <soc/addressmap.h>
+#include <soc/grf.h>
+#include <soc/soc.h>
+#include <stdlib.h>
+
+struct rk3399_gpio_regs *gpio_port[] = {
+	(struct rk3399_gpio_regs *)GPIO0_BASE,
+	(struct rk3399_gpio_regs *)GPIO1_BASE,
+	(struct rk3399_gpio_regs *)GPIO2_BASE,
+	(struct rk3399_gpio_regs *)GPIO3_BASE,
+	(struct rk3399_gpio_regs *)GPIO4_BASE,
+};
+
+enum {
+	PULLNONE = 0,
+	PULLUP,
+	PULLDOWN
+};
+
+#define PMU_GPIO_PORT0 0
+#define PMU_GPIO_PORT1 1
+
+static void __gpio_input(gpio_t gpio, u32 pull)
+{
+	clrbits_le32(&gpio_port[gpio.port]->swporta_ddr, 1 << gpio.num);
+	if (gpio.port == PMU_GPIO_PORT0 || gpio.port == PMU_GPIO_PORT1)
+		clrsetbits_le32(&rk3399_pmugrf->gpio0_p[gpio.port][gpio.bank],
+				3 << (gpio.idx * 2),  pull << (gpio.idx * 2));
+	else
+		write32(&rk3399_grf->gpio2_p[(gpio.port - 2)][gpio.bank],
+			RK_CLRSETBITS(3 << (gpio.idx * 2),
+				   pull << (gpio.idx * 2)));
+}
+
+void gpio_input(gpio_t gpio)
+{
+	__gpio_input(gpio, PULLNONE);
+}
+
+void gpio_input_pulldown(gpio_t gpio)
+{
+	__gpio_input(gpio, PULLDOWN);
+}
+
+void gpio_input_pullup(gpio_t gpio)
+{
+	__gpio_input(gpio, PULLUP);
+}
+
+int gpio_get(gpio_t gpio)
+{
+	return (read32(&gpio_port[gpio.port]->ext_porta) >> gpio.num) & 0x1;
+}
+
+void gpio_output(gpio_t gpio, int value)
+{
+	setbits_le32(&gpio_port[gpio.port]->swporta_ddr, 1 << gpio.num);
+	clrsetbits_le32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num,
+							   !!value << gpio.num);
+}
diff --git a/src/soc/rockchip/rk3399/include/soc/gpio.h b/src/soc/rockchip/rk3399/include/soc/gpio.h
new file mode 100644
index 0000000..cd85be0
--- /dev/null
+++ b/src/soc/rockchip/rk3399/include/soc/gpio.h
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3399_GPIO_H__
+#define __SOC_ROCKCHIP_RK3399_GPIO_H__
+
+#include <types.h>
+
+#define GPIO(p, b, i) ((gpio_t){.port = p, .bank = GPIO_##b, .idx = i})
+
+struct rk3399_gpio_regs {
+	u32 swporta_dr;
+	u32 swporta_ddr;
+	u32 reserved0[(0x30 - 0x08) / 4];
+	u32 inten;
+	u32 intmask;
+	u32 inttype_level;
+	u32 int_polarity;
+	u32 int_status;
+	u32 int_rawstatus;
+	u32 debounce;
+	u32 porta_eoi;
+	u32 ext_porta;
+	u32 reserved1[(0x60 - 0x54) / 4];
+	u32 ls_sync;
+};
+check_member(rk3399_gpio_regs, ls_sync, 0x60);
+
+typedef union {
+	u32 raw;
+	struct {
+		u16 port;
+		union {
+			struct {
+				u16 num:5;
+				u16 :11;
+			};
+			struct {
+				u16 idx:3;
+				u16 bank:2;
+				u16 :11;
+			};
+		};
+	};
+} gpio_t;
+
+enum {
+	GPIO_A = 0,
+	GPIO_B,
+	GPIO_C,
+	GPIO_D,
+};
+
+#endif	/* __SOC_ROCKCHIP_RK3399_GPIO_H__ */