[coreboot-gerrit] New patch to review for coreboot: soc/intel/skylake: add option to enable VR specific mailbox cmd

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13982

-gerrit

commit e7061011fb9024acfef300f9bef7a3e6c103cbf2
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Wed Feb 24 14:31:40 2016 +0530

    soc/intel/skylake: add option to enable VR specific mailbox cmd
    
    Adding an option to enable VR specific mailbox command.
    When set, an extra VR mailbox command specifically for
    the MPS IMPV8 VR will be sent.
    
    BUG=chrome-os-partner:48511
    BRANCH=None
    TEST=Verified on glados, clean S0ix entry and exit.
            IMVP8 power is also pretty low
    
    Change-Id: Ia5a23cbb1eca8b463eb7c7c279b74635f1d6b9f7
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c90a799b51fe35bf184dca6ffce59c89a60f9917
    Original-Change-Id: Iffd3fbcb9a15611eefc942529e6cdafba859fb2e
    Original-Signed-off-by: Robbie Zhang <robbie.zhang at intel.com>
    Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/329393
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/chip.c |  4 ++++
 src/soc/intel/skylake/chip.h | 11 +++++++++--
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index b5bcc65..dbf7785 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -410,6 +410,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 		params->TcoIrqSelect = config->TcoIrqSelect;
 	/* TCO Irq enable/disable */
 	params->TcoIrqEnable = config->TcoIrqEnable;
+	params->SendVrMbxCmd = config->SendVrMbxCmd;
 }
 
 void soc_display_silicon_init_params(const SILICON_INIT_UPD *original,
@@ -1011,6 +1012,9 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *original,
 	fsp_display_upd_value("SerialIoI2cVoltage[5]", 1,
 		original->SerialIoI2cVoltage[5],
 		params->SerialIoI2cVoltage[5]);
+	fsp_display_upd_value("SendVrMbxCmd", 1,
+		original->SendVrMbxCmd,
+		params->SendVrMbxCmd);
 }
 
 static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 6203916..e18b45a 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -312,8 +312,8 @@ struct soc_intel_skylake_config {
 	 */
 	u8 SerialIrqConfigStartFramePulse;
 	u8 FspSkipMpInit;
-
-	/* VrConfig Settings for 5 domains
+	/*
+	 * VrConfig Settings for 5 domains
 	 * 0 = System Agent, 1 = IA Core, 2 = Ring,
 	 * 3 = GT unsliced,  4 = GT sliced
 	 */
@@ -328,6 +328,13 @@ struct soc_intel_skylake_config {
 	u8 PmTimerDisabled;
 	/* Intel Speed Shift Technology */
 	u8 speed_shift_enable;
+	/*
+	 * Enable VR specific mailbox command
+	 * When set, an extra VR mailbox command specifically
+	 * for the MPS IMPV8 VR will be sent.
+	 * 0 - Don't Send, 1 - Send
+	*/
+	u8 SendVrMbxCmd;
 };
 
 typedef struct soc_intel_skylake_config config_t;