[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake: Avoid UART BAR relocation at ramstage

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13997

-gerrit

commit 0ddd944b173cc787e7814d6f5de2cee7722e0d20
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Tue Mar 8 16:12:06 2016 -0800

    soc/intel/apollolake: Avoid UART BAR relocation at ramstage
    
    UART bar gets overwritten during resource allocation stage. As result
    the serial driver ends up using stale BAR so serial output does not
    work. This driver simply tells resource allocator not to change BAR
    of UART device.
    
    Change-Id: I81f4f04089106c80bea97f0bbaba890df00c8ac5
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/Makefile.inc |  1 +
 src/soc/intel/apollolake/uart.c       | 55 +++++++++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+)

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 1b2efdf..8581607 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -32,6 +32,7 @@ ramstage-y += gpio.c
 ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 ramstage-y += memmap.c
 ramstage-y += mmap_boot.c
+ramstage-y += uart.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
 
diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c
new file mode 100644
index 0000000..2040cb0
--- /dev/null
+++ b/src/soc/intel/apollolake/uart.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/*
+ * The sole purpose of this driver is to avoid BAR to be changed during
+ * resource allocation. Since configuration space is just 32 bytes it
+ * shouldn't cause any fragmentation.
+ */
+
+#include <console/uart.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/pci_ids.h>
+
+static void uart_set_resources(struct device *dev)
+{
+	struct resource *res;
+
+	res = new_resource(dev, PCI_BASE_ADDRESS_0);
+	res->base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
+	res->size = 32;
+	res->align = 5;
+	res->gran = 5;
+	res->limit = res->base + res->size - 1;
+	res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_STORED |
+			IORESOURCE_ASSIGNED;
+}
+
+static struct device_operations uart_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = uart_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = pci_dev_init,
+	.enable           = DEVICE_NOOP
+};
+
+static const unsigned short uart_ids[] = {
+	PCI_DEV_ID_APOLLOLAKE_UART2,
+	0
+};
+
+static const struct pci_driver uart_driver __pci_driver = {
+	.ops     = &uart_ops,
+	.vendor  = PCI_VENDOR_ID_INTEL,
+	.devices = uart_ids
+};