[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Add ids of internal SoC PCI devices

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13996

-gerrit

commit 3bdd56ac31db31babf06f82d58e4df6676ea2fc9
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Tue Mar 8 15:57:53 2016 -0800

    soc/intel/apollolake: Add ids of internal SoC PCI devices
    
    Change-Id: I6a632ca7d4a19c4973c41bb102f97e0836f27a5e
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/include/soc/pci_ids.h | 39 ++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h
new file mode 100644
index 0000000..f5bb667
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/pci_ids.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_PCI_IDS_H_
+#define _SOC_APOLLOLAKE_PCI_IDS_H_
+
+#define PCI_DEVICE_ID_APOLLOLAKE_NB		0x5af0		/* 00:00.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_IGD		0x5a84		/* 00:02.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_P2SB		0x5a92		/* 00:0d.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_HWSEQ_SPI	0x5a96		/* 00:0d.2 */
+#define PCI_DEVICE_ID_APOLLOLAKE_AUDIO		0x5a98		/* 00:0e.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_SATA		0x5ae0		/* 00:12.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_I2C0		0x5aac		/* 00:16.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_I2C1		0x5aae		/* 00:16.1 */
+#define PCI_DEVICE_ID_APOLLOLAKE_I2C2		0x5ab0		/* 00:16.2 */
+#define PCI_DEVICE_ID_APOLLOLAKE_I2C3		0x5ab2		/* 00:16.3 */
+#define PCI_DEVICE_ID_APOLLOLAKE_I2C4		0x5ab4		/* 00:17.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_I2C5		0x5ab6		/* 00:17.1 */
+#define PCI_DEVICE_ID_APOLLOLAKE_I2C6		0x5ab8		/* 00:17.2 */
+#define PCI_DEVICE_ID_APOLLOLAKE_I2C7		0x5aba		/* 00:17.3 */
+#define PCI_DEVICE_ID_APOLLOLAKE_UART0		0x5abc		/* 00:18.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_UART1		0x5abe		/* 00:18.1 */
+#define PCI_DEVICE_ID_APOLLOLAKE_UART2		0x5ac0		/* 00:18.2 */
+#define PCI_DEVICE_ID_APOLLOLAKE_UART3		0x5aee		/* 00:18.3 */
+#define PCI_DEVICE_ID_APOLLOLAKE_SPI0		0x5ac2		/* 00:19.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_SPI1		0x5ac4		/* 00:19.1 */
+#define PCI_DEVICE_ID_APOLLOLAKE_SPI2		0x5ac6		/* 00:19.2 */
+#define PCI_DEVICE_ID_APOLLOLAKE_LPC		0x5ae8		/* 00:1f.0 */
+
+#endif /* _SOC_APOLLOLAKE_PCI_IDS_H_ */