[coreboot-gerrit] Patch merged into coreboot/master: nb/amd/mct_ddr3: Require minumum training quality for both read and write

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 2e1f73181a770f1c3a8ea5bc1b72bac3732c5c76
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Tue Mar 8 16:44:39 2016 -0600

    nb/amd/mct_ddr3: Require minumum training quality for both read and write
    
    The existing MCT code proceeded to the next DRAM training phase if
    the minimum lane quality standard passed for either the read or
    write direction.  Ensure that both pass for a given set of delay
    values before proceeding to the next training phase.
    
    Change-Id: I2316ca639f58a23cf64bea56290e9422e02edf1c
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
    Reviewed-on: https://review.coreboot.org/13993
    Tested-by: Raptor Engineering Automated Test Stand <noreply at raptorengineeringinc.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/13993 for details.

-gerrit