[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: enable RAM cache for cbmem region in ramstage

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14095

-gerrit

commit b9d2cef9abf46a6f8fea15cbf9d3d097bdf804ec
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Sun Mar 13 16:01:55 2016 -0700

    soc/intel/apollolake: enable RAM cache for cbmem region in ramstage
    
    Since ramstage code as well as FSP code is run in cbmem that is
    placed in DRAM, it is imporant to have that region cached for
    performance reasons. This patch enables WB cache for 16MiB below
    cbmem top which is a safe bet ramstage is covered.
    
    Change-Id: I3f2f6e82f3b9060c7350ddff754cd3dbcf457671
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/romstage.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 7c8924d..45899fd 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -15,6 +15,7 @@
 #include <arch/symbols.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <cpu/x86/mtrr.h>
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <fsp/api.h>
@@ -80,6 +81,7 @@ asmlinkage void car_stage_entry(void)
 	void *hob_list_ptr;
 	struct range_entry fsp_mem;
 	struct range_entry reg_car;
+	uintptr_t top_of_ram;
 
 	printk(BIOS_DEBUG, "Starting romstage...\n");
 
@@ -95,6 +97,24 @@ asmlinkage void car_stage_entry(void)
 		die("FSP memory init failed. Giving up.");
 	}
 
+	/*
+	 * Cache 16 MiB area right below cbmem, so that ramstage and FSP
+	 * reserved memory ran cached. This assumes address is at least
+	 * 16 MiB aligned.
+	 *
+	 * After this call we get:
+	 * - Non-evict mode (NEM) is enabled
+	 * - Write-back cache is active for small window in DRAM
+	 *
+	 * Since NEM mode blocks cache fills, memory operations do not make
+	 * it into L2 cache. L1D cache however works in normal mode. Since
+	 * L1 size is smaller than the actual working set, we are slower than
+	 * fully fledged L2. However it is still about 10x faster than non-
+	 * cached memory.
+	 */
+	top_of_ram = (uintptr_t) cbmem_top();
+	set_var_mtrr(1, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
+
 	fsp_find_reserved_memory(&fsp_mem, hob_list_ptr);
 
 	/* initialize cbmem by adding FSP reserved memory first thing */