[coreboot-gerrit] Patch merged into coreboot/master: skylake mainboards: Configure gpio PADRSTCFG to PLTRST

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 1a1515b949ef759729a217faf5e8274ec3f3cb5f
Author: Naresh G Solanki <naresh.solanki at intel.com>
Date:   Mon Feb 29 13:20:44 2016 +0530

    skylake mainboards: Configure gpio PADRSTCFG to PLTRST
    
    With gpio PADRSTCFG set to DEEP & GPIROUTIOXAPIC=1 & PADRSTCFG, causes
    IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get
    their logic reset over pltrst and hence configuring PADRSTCFG to
    PLTRST to prevent IRQ strom after S3 resume.
    
    BRANCH=glados
    BUG=chrome-os-partner:50536
    TEST=Build for kunimitsu and Boot on FAB4, no irq storm observed
    after S3 resume.
    
    Change-Id: I7f1ae90aed03778e7d6cb2d79de0efe9a6d9e20d
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: aff91da4feaf8f7e42cfeee756cf468288cbfd68
    Original-Change-Id: I7cac60fb0144e090b8decb05d948b2d8d2f8deac
    Original-Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/329453
    Original-Commit-Ready: Naresh Solanki <naresh.solanki at intel.com>
    Original-Tested-by: Naresh Solanki <naresh.solanki at intel.com>
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/331174
    Original-Commit-Ready: Patrick Georgi <pgeorgi at chromium.org>
    Original-Tested-by: Patrick Georgi <pgeorgi at chromium.org>
    Reviewed-on: https://review.coreboot.org/13992
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See https://review.coreboot.org/13992 for details.

-gerrit