[coreboot-gerrit] New patch to review for coreboot: intel/fsp1_1: Do not re-init TPM in romstage if already setup in verstage

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14106

-gerrit

commit 4c2f3e3a9e9ba4fddbc0818eed6756aba36b604a
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Mar 14 09:29:09 2016 -0700

    intel/fsp1_1: Do not re-init TPM in romstage if already setup in verstage
    
    For platforms that do verification of memory init (and have verstage
    execute before romstage) FSP should not attempt to re-initialize the
    TPM again in romstage as it has already been done.
    
    BUG=chrome-os-partner:50633
    BRANCH=glados
    TEST=boot and resume on chell and ensure TPM is not re-initialized
    
    Change-Id: Ied6f39dc8dacdbc3d76070b6135de2308196ff53
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: fefd4d4b3fde4c7fe4b6de304790914b7a2f87d8
    Original-Change-Id: I60a2e4e2d73270697218f094527e09d444e6ab56
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Previous-Reviewed-on: https://chromium-review.googlesource.com/332433
    Original-(cherry picked from commit 2de1fd57fe1db7960e0bb86c64dccf827fa55742)
    Original-Reviewed-on: https://chromium-review.googlesource.com/332299
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/drivers/intel/fsp1_1/romstage.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index bf84d66..3d698bb 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -173,8 +173,15 @@ void romstage_common(struct romstage_params *params)
 		hard_reset();
 	}
 
-	if (IS_ENABLED(CONFIG_LPC_TPM))
-		init_tpm(params->power_state->prev_sleep_state == SLEEP_STATE_S3);
+	/*
+	 * Initialize the TPM, unless the TPM was already initialized
+	 * in verstage and used to verify romstage.
+	 */
+	if (IS_ENABLED(CONFIG_LPC_TPM) &&
+	    !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) &&
+	    !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))
+		init_tpm(params->power_state->prev_sleep_state ==
+			 SLEEP_STATE_S3);
 }
 
 void after_cache_as_ram_stage(void)