[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake: Fix MMIO reserved ranges calculation

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14203

-gerrit

commit 9e90d6c02264f73a2ae5c8fc73d3f32670e3e447
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Wed Mar 30 18:15:30 2016 -0700

    soc/intel/apollolake: Fix MMIO reserved ranges calculation
    
    mmio_resource() takes memory address in kilobytes. This patch
    adds resources properly.
    
    Change-Id: Id78dcecf05ad5b2c84e5bb5445ae3a4e4ec9d419
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/northbridge.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c
index 35c36c8..7d29c9e 100644
--- a/src/soc/intel/apollolake/northbridge.c
+++ b/src/soc/intel/apollolake/northbridge.c
@@ -30,13 +30,15 @@ static uint32_t get_bar(device_t dev, unsigned int index)
 
 static int mc_add_fixed_mmio_resources(device_t dev, int index)
 {
+	unsigned long addr;
+
 	/* PCI extended config region */
-	mmio_resource(dev, index++, ALIGN_DOWN(get_bar(dev, PCIEXBAR), 256*MiB),
-						PCIEX_SIZE / KiB);
+	addr = ALIGN_DOWN(get_bar(dev, PCIEXBAR), 256*MiB) / KiB;
+	mmio_resource(dev, index++, addr, PCIEX_SIZE / KiB);
 
 	/* Memory Controller Hub */
-	mmio_resource(dev, index++, ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB),
-						MCH_BASE_SIZE / KiB);
+	addr = ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB) / KiB;
+	mmio_resource(dev, index++, addr, MCH_BASE_SIZE / KiB);
 
 	return index;
 }