[coreboot-gerrit] New patch to review for coreboot: soc/intel/broadwell: transition away from device_t

[Antonello Dettori (dev@dettori.io)]

Antonello Dettori (dev at dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17318

-gerrit

commit 47969ebfc27bda9d4c8cd78095b3c7b16ba69569
Author: Antonello Dettori <dev at dettori.io>
Date:   Tue Nov 8 18:44:46 2016 +0100

    soc/intel/broadwell: transition away from device_t
    
    Replace the use of the old device_t definition inside
    soc/intel/broadwell.
    
    Change-Id: Ibadf383f81e78e160749f1811b6224b417d2a1f9
    Signed-off-by: Antonello Dettori <dev at dettori.io>
---
 src/soc/intel/broadwell/include/soc/pch.h      |  3 +++
 src/soc/intel/broadwell/include/soc/ramstage.h |  3 +++
 src/soc/intel/broadwell/romstage/pch.c         | 12 ++++++++++++
 3 files changed, 18 insertions(+)

diff --git a/src/soc/intel/broadwell/include/soc/pch.h b/src/soc/intel/broadwell/include/soc/pch.h
index 690af9f..4dfd1bb 100644
--- a/src/soc/intel/broadwell/include/soc/pch.h
+++ b/src/soc/intel/broadwell/include/soc/pch.h
@@ -43,6 +43,9 @@ int pch_is_wpt(void);
 int pch_is_wpt_ulx(void);
 u32 pch_read_soft_strap(int id);
 void pch_log_state(void);
+
+#ifndef __SIMPLE_DEVICE__
 void pch_disable_devfn(device_t dev);
+#endif
 
 #endif
diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h
index db67fe3..c68a4c9 100644
--- a/src/soc/intel/broadwell/include/soc/ramstage.h
+++ b/src/soc/intel/broadwell/include/soc/ramstage.h
@@ -20,8 +20,11 @@
 #include <soc/intel/broadwell/chip.h>
 
 void broadwell_init_pre_device(void *chip_info);
+
+#ifndef __SIMPLE_DEVICE__
 void broadwell_init_cpus(device_t dev);
 void broadwell_pch_enable_dev(device_t dev);
+#endif
 
 #if CONFIG_HAVE_REFCODE_BLOB
 void broadwell_run_reference_code(void);
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c
index 74d3125..9a07c77 100644
--- a/src/soc/intel/broadwell/romstage/pch.c
+++ b/src/soc/intel/broadwell/romstage/pch.c
@@ -131,6 +131,17 @@ static void pch_enable_lpc(void)
 	pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec);
 }
 
+#ifdef __SIMPLE_DEVICE__
+static void pcie_update_cfg(pci_devfn_t dev, int reg, u32 mask, u32 or)
+{
+	u32 reg32;
+
+	reg32 = pci_read_config32(dev, reg);
+	reg32 &= mask;
+	reg32 |= or;
+	pci_write_config32(dev, reg, reg32);
+}
+#else
 static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or)
 {
 	u32 reg32;
@@ -140,6 +151,7 @@ static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or)
 	reg32 |= or;
 	pci_write_config32(dev, reg, reg32);
 }
+#endif
 
 void pch_early_init(void)
 {