[coreboot-gerrit] New patch to review for coreboot: soc/intel/skylake: Disable Legacy PME for Root ports
Naresh Solanki (naresh.solanki@intel.com)
gerrit at coreboot.org
Mon Nov 21 13:32:17 CET 2016
Naresh Solanki (naresh.solanki at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17553
-gerrit
commit 3166af37323557540516b784129c58d184008cd0
Author: Naresh G Solanki <naresh.solanki at intel.com>
Date: Wed Nov 16 21:27:38 2016 +0530
soc/intel/skylake: Disable Legacy PME for Root ports
In FSP we are also enabling the Legacy PME handling, where an SCI is generated
and should be handled by OS and BIOS/Coreboot in collboration. OS requires some
ACPI methods (eg _L69) which help to determine the wake source and also to clear
some registers.But this infrastructure is not present as of now in coreboot and
also linux handles PMEs natively.
Hence the SCI was never handled by OS and the status bits were never cleared ie
PCI_EXP_STS.
For this reason the level triggered SCI will remain active and the system will
wake up as soon as it enters S3.
To fix this, diabled Legacy PME (PmSci for Root ports).
Change-Id: I61317eb45305bdb14be3cc1a54fd9961d6ed593e
Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
---
src/soc/intel/skylake/chip_fsp20.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 49569d9..8ef3cf4 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -148,6 +148,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber,
sizeof(params->PcieRpClkReqNumber));
+ /* disable Legacy PME */
+ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
+
memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
sizeof(params->SerialIoDevMode));
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