[coreboot-gerrit] Patch set updated for coreboot: src/southbridge: Remove unnecessary semicolon
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Mon Oct 3 20:56:34 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16857
-gerrit
commit fe13dd22ebf61d12df245df02c6a0740655aa912
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Mon Oct 3 20:41:04 2016 +0200
src/southbridge: Remove unnecessary semicolon
Change-Id: I52c3ec75d44290b758b6e952344aa9a768bc2617
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/southbridge/amd/cimx/sb700/smbus_spd.c | 2 +-
src/southbridge/amd/rs690/pcie.c | 2 +-
src/southbridge/amd/sb600/early_setup.c | 4 ++--
src/southbridge/amd/sb700/early_setup.c | 2 +-
src/southbridge/amd/sb800/early_setup.c | 2 +-
src/southbridge/nvidia/mcp55/smbus.h | 4 ++--
src/southbridge/sis/sis966/early_smbus.c | 4 ++--
7 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/southbridge/amd/cimx/sb700/smbus_spd.c b/src/southbridge/amd/cimx/sb700/smbus_spd.c
index 281279b..73261c4 100644
--- a/src/southbridge/amd/cimx/sb700/smbus_spd.c
+++ b/src/southbridge/amd/cimx/sb700/smbus_spd.c
@@ -120,7 +120,7 @@ static void setupFch(UINT16 ioBase)
/* Enable SMBus MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2);
- LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ;
+ LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader);
PciData8 |= BIT0;
LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader);
diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c
index 043c2ee..db65686 100644
--- a/src/southbridge/amd/rs690/pcie.c
+++ b/src/southbridge/amd/rs690/pcie.c
@@ -310,7 +310,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
/* step 6d: ASPM L1 for the southbridge link */
/* To enable L1s in the southbridge*/
- /* step 6e: ASPM L1 for GPP link(s) */;
+ /* step 6e: ASPM L1 for GPP link(s) */
set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13);
set_pcie_enable_bits(dev, 0xa0, 3 << 12, 3 << 12);
set_pcie_enable_bits(dev, 0xa0, 0xf << 4, 3 << 4);
diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c
index 2caa28b..2445310 100644
--- a/src/southbridge/amd/sb600/early_setup.c
+++ b/src/southbridge/amd/sb600/early_setup.c
@@ -370,13 +370,13 @@ static void sb600_devices_por_init(void)
printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
/* I don't know why CIM tried to write into a read-only reg! */
- /*pci_write_config8(dev, 0x0c, 0x20) */ ;
+ /*pci_write_config8(dev, 0x0c, 0x20); */
/* Arbiter enable. */
pci_write_config8(dev, 0x43, 0xff);
/* Set PCDMA request into height priority list. */
- /* pci_write_config8(dev, 0x49, 0x1) */ ;
+ /* pci_write_config8(dev, 0x49, 0x1); */
pci_write_config8(dev, 0x40, 0x26);
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index ea7eb27..631f252 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -520,7 +520,7 @@ static void sb700_devices_por_init(void)
pci_write_config8(dev, 0x43, 0xff);
/* Set PCDMA request into height priority list. */
- /* pci_write_config8(dev, 0x49, 0x1) */ ;
+ /* pci_write_config8(dev, 0x49, 0x1) */
pci_write_config8(dev, 0x40, 0x26);
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index 1096159..cf5490e 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -468,7 +468,7 @@ static void sb800_devices_por_init(void)
pci_write_config8(dev, 0x43, 0xff);
/* Set PCDMA request into height priority list. */
- /* pci_write_config8(dev, 0x49, 0x1) */ ;
+ /* pci_write_config8(dev, 0x49, 0x1) */
pci_write_config8(dev, 0x40, 0x26);
diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h
index 8f2884a..a7a6679 100644
--- a/src/southbridge/nvidia/mcp55/smbus.h
+++ b/src/southbridge/nvidia/mcp55/smbus.h
@@ -102,7 +102,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned
if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3;
}
- global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
+ global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
if (global_status_register != 0x80) {
return -1;
@@ -163,7 +163,7 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned
if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3;
}
- global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
+ global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
if (global_status_register != 0x80) {
return -1;
diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c
index 5ccceda..99f8bd4 100644
--- a/src/southbridge/sis/sis966/early_smbus.c
+++ b/src/southbridge/sis/sis966/early_smbus.c
@@ -109,7 +109,7 @@ int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char va
if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3;
}
- global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
+ global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
if (global_status_register != 0x80) {
return -1;
@@ -176,7 +176,7 @@ static inline int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, u
if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3;
}
- global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
+ global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
if (global_status_register != 0x80) {
return -1;
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