[coreboot-gerrit] New patch to review for coreboot: northbridge/intel/i440bx: Remove commented code
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Tue Oct 4 20:48:14 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16878
-gerrit
commit 268cc5ed35d6c0a4613e5be404562cec7d65525a
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Tue Oct 4 20:44:48 2016 +0200
northbridge/intel/i440bx: Remove commented code
Change-Id: I0dd8c32f1b9165fe8c449cee1c21a155a725c04f
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/northbridge/intel/i440bx/raminit.c | 16 ----------------
1 file changed, 16 deletions(-)
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 66282aa..f9fd816 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -423,11 +423,6 @@ static void do_ram_command(u32 command)
addr = (void *)((dimm_start * 8 * 1024 * 1024) + addr_offset);
if (dimm_end > dimm_start) {
-#if 0
- PRINT_DEBUG(" Sending RAM command 0x%04x to 0x%08x\n",
- reg16, addr);
-#endif
-
read32(addr);
}
@@ -634,10 +629,6 @@ void sdram_set_registers(void)
reg &= register_values[i + 1];
reg |= register_values[i + 2] & ~(register_values[i + 1]);
pci_write_config8(NB, register_values[i], reg);
-#if 0
- PRINT_DEBUG(" Set register 0x%02x to 0x%02x\n",
- register_values[i], reg);
-#endif
}
}
@@ -885,10 +876,6 @@ static void set_dram_row_attributes(void)
drb &= 0xff;
drb |= (drb + (sz.side2 / 8)) << 8;
} else {
-#if 0
- PRINT_DEBUG("No DIMM found in slot %d\n", i);
-#endif
-
/* If there's no DIMM in the slot, set dra to 0x00. */
dra = 0x00;
/* Still have to propagate DRB over. */
@@ -897,9 +884,6 @@ static void set_dram_row_attributes(void)
}
pci_write_config16(NB, DRB + (2 * i), drb);
-#if 0
- PRINT_DEBUG("DRB has been set to 0x%04x\n", drb);
-#endif
/* Brings the upper DRB back down to be base for
* DRB calculations for the next two rows.
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