[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Disable HECI2 device reset on S3 resume

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16870

-gerrit

commit 615f4ada62cc0a01d95876994481580af1d19d2e
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Mon Oct 3 16:05:20 2016 -0700

    soc/intel/apollolake: Disable HECI2 device reset on S3 resume
    
    Convered Security Engine (CSE)  has a secure variable storage feature.
    However, this storage is expected to be reset during S3 resume flow.
    Since coreboot does not use secure storage feature, disable HECI2 reset
    request. This saves appr. 130ms of resume time.
    
    BUG=chrome-os-partner:56941
    BRANCH=none
    TEST=powerd_dbus_suspend; resume; check time with cbmem -t. Note
    FspMemoryInit time is not significantly different from normal boot
    time case.
    
    Change-Id: I485a980369c6bd97c43b9e554d65ee89e84d8233
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/romstage.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index b9733de..c1e6dc8 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -169,6 +169,15 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd)
 	 */
 	mupd->FspmConfig.SkipCseRbp =
 		IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED);
+
+	/*
+	 * Convered Security Engine (CSE) has secure storage functionality.
+	 * HECI2 device can be used to access that functionality. However, part
+	 * of S3 resume flow involves resetting HECI2 which takes 136ms. Since
+	 * coreboot does not use secure storage functionality, instruct FSP to
+	 * skip HECI2 reset.
+	 */
+	mupd->FspmConfig.EnableS3Heci2 = 0;
 }
 
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