[coreboot-gerrit] Patch set updated for coreboot: spi: Add a way to show SPI transfer speed for reads

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16701

-gerrit

commit 3a91a3a676a9e71064ae33bcaf0fefd5917aa1ba
Author: Simon Glass <sjg at chromium.org>
Date:   Sat Aug 27 15:03:02 2016 -0600

    spi: Add a way to show SPI transfer speed for reads
    
    SPI read speed directly impacts boot time and we do quite a lot of
    reading.
    
    Add a way to easily find out the speed of SPI flash reads within
    coreboot.
    
    Write speed is less important since there are very few writes and they
    are small.
    
    BUG=chrome-os-partner:56556
    BRANCH=none
    TEST=run on gru with SPI_SPEED_DEBUG set to 1. See the output messages:
    read SPI 627d4 7d73: 18455 us, 1740 KB/s, 13.920 Mbps
    
    Change-Id: Id3814bd2b7bd045cdfcc67eb1fabc861bf9ed3b2
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 82cb93f6be47efce3b0a3843bab89d2381baef89
    Original-Change-Id: Iec66f5b8e3ad62f14d836a538dc7801e4ca669e7
    Original-Signed-off-by: Simon Glass <sjg at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/376944
    Original-Commit-Ready: Julius Werner <jwerner at chromium.org>
    Original-Tested-by: Simon Glass <sjg at google.com>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
 src/drivers/spi/cbfs_spi.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/src/drivers/spi/cbfs_spi.c b/src/drivers/spi/cbfs_spi.c
index 1895b9d..46e7346 100644
--- a/src/drivers/spi/cbfs_spi.c
+++ b/src/drivers/spi/cbfs_spi.c
@@ -23,14 +23,44 @@
 #include <spi_flash.h>
 #include <symbols.h>
 #include <cbmem.h>
+#include <timer.h>
 
 static struct spi_flash *spi_flash_info;
 
+/*
+ * Set this to 1 to debug SPI speed, 0 to disable it
+ * The format is:
+ *
+ * read SPI 62854 7db7: 10416 us, 3089 KB/s, 24.712 Mbps
+ *
+ * The important number is the last one. It should roughly match your SPI
+ * clock. If it doesn't, your driver might need a little tuning.
+ */
+#define SPI_SPEED_DEBUG		0
+
 static ssize_t spi_readat(const struct region_device *rd, void *b,
 				size_t offset, size_t size)
 {
+	struct stopwatch sw;
+	bool show = SPI_SPEED_DEBUG && size >= 4 * KiB;
+
+	if (show)
+		stopwatch_init(&sw);
 	if (spi_flash_info->read(spi_flash_info, offset, size, b))
 		return -1;
+	if (show) {
+		long usecs;
+
+		usecs = stopwatch_duration_usecs(&sw);
+		u64 speed;	/* KiB/s */
+		int bps;	/* Bits per second */
+
+		speed = (u64)size * 1000 / usecs;
+		bps = speed * 8;
+
+		printk(BIOS_DEBUG, "read SPI %#zx %#zx: %ld us, %lld KB/s, %d.%03d Mbps\n",
+		       offset, size, usecs, speed, bps / 1000, bps % 1000);
+	}
 	return size;
 }