[coreboot-gerrit] Patch set updated for coreboot: rockchip/rk3399: Configure USB3 controller work in USB2 only mode
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Tue Oct 4 21:29:09 CEST 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16717
-gerrit
commit 0bcdfb76da297fa3050ad6ce2f8c6e5f4b1be59a
Author: Liangfeng Wu <wulf at rock-chips.com>
Date: Thu Sep 15 17:16:54 2016 +0800
rockchip/rk3399: Configure USB3 controller work in USB2 only mode
During the USB2 only mode, the Type-C PHY will be held in reset
and only USB2 part logic of USB3 OTG controller and PHY may be
used over the USB2 pins on the Type-C connector to support Low,
Full and High-speed USB operation.
BRANCH=none
BUG=chrome-os-partner:56425
TEST=Go to recovery mode, plug a Type-C USB drive containing
chrome OS image into both ports in all orientations, check if
system can boot form USB.
Change-Id: Ic265c0c91c24f63b2f9c3106eb2bb277a589233b
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: a37ccc5b6019967483eac6b5a360d67bc3326e93
Original-Change-Id: I582f04f84eef447ff0ba691ce60e9461ed31cfad
Original-Signed-off-by: Liangfeng Wu <wulf at rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/385837
Original-Commit-Ready: Julius Werner <jwerner at chromium.org>
Original-Tested-by: Julius Werner <jwerner at chromium.org>
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
src/soc/rockchip/rk3399/usb.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/src/soc/rockchip/rk3399/usb.c b/src/soc/rockchip/rk3399/usb.c
index f638a1e..4c731bd 100644
--- a/src/soc/rockchip/rk3399/usb.c
+++ b/src/soc/rockchip/rk3399/usb.c
@@ -17,6 +17,9 @@
#include <assert.h>
#include <console/console.h>
#include <delay.h>
+#include <soc/clock.h>
+#include <soc/grf.h>
+#include <soc/soc.h>
#include <soc/usb.h>
/* SuperSpeed over Type-C is hard. We don't care about speed in firmware: just
@@ -86,12 +89,24 @@ static void setup_dwc3(struct rockchip_usb_dwc3 *dwc3)
void reset_usb_otg0(void)
{
+ /* Keep whole USB OTG0 controller in reset, then
+ * configure controller to work in USB 2.0 only mode. */
+ write32(&cru_ptr->softrst_con[18], RK_SETBITS(1 << 5));
+ write32(&rk3399_grf->usb3otg0_con1, RK_CLRSETBITS(0xf << 12, 1 << 0));
+ write32(&cru_ptr->softrst_con[18], RK_CLRBITS(1 << 5));
+
printk(BIOS_DEBUG, "Starting DWC3 reset for USB OTG0\n");
reset_dwc3(rockchip_usb_otg0_dwc3);
}
void reset_usb_otg1(void)
{
+ /* Keep whole USB OTG1 controller in reset, then
+ * configure controller to work in USB 2.0 only mode. */
+ write32(&cru_ptr->softrst_con[18], RK_SETBITS(1 << 6));
+ write32(&rk3399_grf->usb3otg1_con1, RK_CLRSETBITS(0xf << 12, 1 << 0));
+ write32(&cru_ptr->softrst_con[18], RK_CLRBITS(1 << 6));
+
printk(BIOS_DEBUG, "Starting DWC3 reset for USB OTG1\n");
reset_dwc3(rockchip_usb_otg1_dwc3);
}
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