[coreboot-gerrit] New patch to review for coreboot: src/northbridge/via: Remove commented code
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Wed Oct 5 21:32:06 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16898
-gerrit
commit d9ab95e44cf489956801328dffa243f5766382d4
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Wed Oct 5 21:02:23 2016 +0200
src/northbridge/via: Remove commented code
Change-Id: Ic589b26c6c94df12e1fe218d079018db8b38fbd9
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/northbridge/via/cx700/raminit.c | 8 --
src/northbridge/via/vx800/drdy_bl.c | 89 ----------------------
src/northbridge/via/vx800/ide.c | 54 --------------
src/northbridge/via/vx800/lpc.c | 18 -----
src/northbridge/via/vx800/northbridge.c | 16 ----
src/northbridge/via/vx800/uma_ram_setting.c | 112 ----------------------------
src/northbridge/via/vx800/vga.c | 20 -----
7 files changed, 317 deletions(-)
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c
index aad851d..f8d709c 100644
--- a/src/northbridge/via/cx700/raminit.c
+++ b/src/northbridge/via/cx700/raminit.c
@@ -815,7 +815,6 @@ static void sdram_set_safe_values(const struct mem_controller *ctrl)
/* Clock Phase Control for FeedBack Mode */
regs = pci_read_config8(MEMCTRL, 0x90);
-// regs |= 0x80;
pci_write_config8(MEMCTRL, 0x90, regs);
regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ);
@@ -1343,13 +1342,6 @@ static void sdram_enable(const struct mem_controller *ctrl)
/****************************************************************/
/* Find out the lowest Bank Interleave and Set Register */
/****************************************************************/
-#if 0
- //TODO
- reg8 = pci_read_config8(MEMCTRL, 0x69);
- reg8 &= ~0xc0;
- reg8 |= 0x80; //8 banks
- pci_write_config8(MEMCTRL, 0x69, reg8);
-#endif
dl = 2;
for (i = 0; i < 4; i++) {
reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
diff --git a/src/northbridge/via/vx800/drdy_bl.c b/src/northbridge/via/vx800/drdy_bl.c
index 0c5f63c..73d897a 100644
--- a/src/northbridge/via/vx800/drdy_bl.c
+++ b/src/northbridge/via/vx800/drdy_bl.c
@@ -439,101 +439,12 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr)
Data |= 0x08;
pci_write_config8(PCI_DEV(0, 0, 2), 0x54, Data);
- //Data = pci_read_config8(PCI_DEV(0,0,2), 0x55);
- //Data = Data & (~0x20);
- //pci_write_config8(PCI_DEV(0,0,2), 0x55, Data);
-
//enable drdy timing
Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x51);
Data = Data | 0x80;
pci_write_config8(PCI_DEV(0, 0, 2), 0x51, Data);
#endif
-#if 0 //default
- {
- //disable drdy timing
- Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x51);
- Data = Data & 0x7F;
- pci_write_config8(PCI_DEV(0, 0, 2), 0x51, Data);
- }
-#endif
-#if 0 // 2:Optimize
- u8 CpuFreq, DramFreq;
- u8 CL, RDRPH;
-
- //CL :reg6x[2:0]
- Data = pci_read_config8(MEMCTRL, 0x62);
- CL = Data & 0x07;
-
- //RDRPH: reg7B[6:4]
- Data = pci_read_config8(MEMCTRL, 0x7B);
- RDRPH = (Data & 0x70) >> 4;
-
- //CpuFreq: F2Reg54[7:5]
- Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x54);
- CpuFreq = (Data & 0xE0) >> 5;
-
- //DramFreq:F3Reg90[2:0]
- Data = pci_read_config8(MEMCTRL, 0x90);
- DramFreq = Data & 0x07;
-
- u8 DelayMode;
- DelayMode = CL + RDRPH; // RDELAYMD = bit0 of (CAS Latency + RDRPH)
- DelayMode &= 0x01;
- u8 ProgData[PT894_RDRDY_TBL_Width];
-
- //In 364, there is no 128 bit
- if (DelayMode == 1) { // DelayMode 1
- u8 Index;
- for (Index = 0; Index < PT894_RDRDY_TBL_Width; Index++)
- ProgData[Index] =
- PT894_64bit_DELAYMD1_RCONV0[CpuFreq][DramFreq]
- [Index];
- } else { // DelayMode 0
- u8 Index;
- for (Index = 0; Index < PT894_RDRDY_TBL_Width; Index++)
- ProgData[Index] =
- PT894_64bit_DELAYMD0_RCONV0[CpuFreq][DramFreq]
- [Index];
- }
-
- Data = ProgData[0];
- pci_write_config8(PCI_DEV(0, 0, 2), 0x60, Data);
-
- Data = ProgData[1];
- pci_write_config8(PCI_DEV(0, 0, 2), 0x61, Data);
-
- Data = ProgData[2];
- pci_write_config8(PCI_DEV(0, 0, 2), 0x62, Data);
-
- Data = ProgData[3];
- pci_write_config8(PCI_DEV(0, 0, 2), 0x63, Data);
-
- Data = ProgData[4];
- pci_write_config8(PCI_DEV(0, 0, 2), 0x64, Data);
-
- Data = ProgData[5];
- pci_write_config8(PCI_DEV(0, 0, 2), 0x65, Data);
-
- Data = ProgData[6];
- pci_write_config8(PCI_DEV(0, 0, 2), 0x66, Data);
-
- Data = ProgData[7];
- pci_write_config8(PCI_DEV(0, 0, 2), 0x67, Data);
-
- Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x54);
- Data = (Data & 0xF5) | ProgData[8];
- pci_write_config8(PCI_DEV(0, 0, 2), 0x54, Data);
-
- Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x55);
- Data = Data & (~0x22) | ProgData[9];
- pci_write_config8(PCI_DEV(0, 0, 2), 0x62, Data);
-
- //enable drdy timing
- Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x51);
- Data = Data | 0x80;
- pci_write_config8(PCI_DEV(0, 0, 2), 0x51, Data);
-#endif
}
/*This routine process the ability for North Bridge side burst functionality
diff --git a/src/northbridge/via/vx800/ide.c b/src/northbridge/via/vx800/ide.c
index 3fb2c23..d2cdb51 100644
--- a/src/northbridge/via/vx800/ide.c
+++ b/src/northbridge/via/vx800/ide.c
@@ -172,7 +172,6 @@ static void ide_init(struct device *dev)
for (i = 0; i < (16 * 12); i++) {
pci_write_config8(dev, 0x40 + i, idedevicepcitable[i]);
}
- //pci_write_config8(dev, 0x0d, 0x20);
data = pci_read_config8(dev, 0x0d);
data &= 0x0f;
data |= 0x40;
@@ -185,59 +184,6 @@ static void ide_init(struct device *dev)
/* Force interrupts to use compat mode. */
pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0);
pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff);
-#if 0
- u8 enables;
- u32 cablesel;
-
- pci_write_config16(dev, 0x04, 0x0007);
-
- enables = pci_read_config8(dev, IDE_CS) & ~0x3;
- enables |= 0x02;
- pci_write_config8(dev, IDE_CS, enables);
- enables = pci_read_config8(dev, IDE_CS);
- printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables);
-
- /* Enable only compatibility mode. */
- enables = pci_read_config8(dev, IDE_CONF_II);
- enables &= ~0xc0;
- pci_write_config8(dev, IDE_CONF_II, enables);
- enables = pci_read_config8(dev, IDE_CONF_II);
- printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables);
-
- /* Enable prefetch buffers. */
- enables = pci_read_config8(dev, IDE_CONF_I);
- enables |= 0xf0;
- pci_write_config8(dev, IDE_CONF_I, enables);
-
- /* Flush FIFOs at half. */
- enables = pci_read_config8(dev, IDE_CONF_FIFO);
- enables &= 0xf0;
- enables |= (1 << 2) | (1 << 0);
- pci_write_config8(dev, IDE_CONF_FIFO, enables);
-
- /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */
- enables = pci_read_config8(dev, IDE_MISC_I);
- enables &= 0xe2;
- enables |= (1 << 4) | (1 << 3);
- pci_write_config8(dev, IDE_MISC_I, enables);
-
- /* Use memory read multiple, Memory-Write-and-Invalidate. */
- enables = pci_read_config8(dev, IDE_MISC_II);
- enables |= (1 << 2) | (1 << 3);
- pci_write_config8(dev, IDE_MISC_II, enables);
-
- /* Force interrupts to use compat mode. */
- pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0);
- pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff);
-
- /* Cable guy... */
- cablesel = pci_read_config32(dev, IDE_UDMA);
- cablesel &= ~((1 << 28) | (1 << 20) | (1 << 12) | (1 << 4));
- cablesel |= (sb->ide0_80pin_cable << 28) |
- (sb->ide0_80pin_cable << 20) |
- (sb->ide1_80pin_cable << 12) | (sb->ide1_80pin_cable << 4);
- pci_write_config32(dev, IDE_UDMA, cablesel);
-#endif
}
static struct device_operations ide_ops = {
diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c
index 4279796..1ab11c0 100644
--- a/src/northbridge/via/vx800/lpc.c
+++ b/src/northbridge/via/vx800/lpc.c
@@ -83,11 +83,9 @@ static void pci_routing_fixup(struct device *dev)
/* PCI slot */
printk(BIOS_INFO, "setting ide\n");
- //pci_assign_irqs(0, 0x0f, pin_to_irq(idePins));
/* Standard usb components */
printk(BIOS_INFO, "setting usb1-2\n");
-// pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
/* sound hardware */
printk(BIOS_INFO, "setting hdac audio\n");
@@ -109,7 +107,6 @@ static void setup_pm(device_t dev)
pci_write_config8(dev, 0x82, 0x49);
/* Primary interupt channel, define wake events 0 = IRQ0 15 = IRQ15 1 = en. */
-// pci_write_config16(dev, 0x84, 0x30f2);
pci_write_config16(dev, 0x84, 0x609a); // 0x609a??
/* SMI output level to low, 7.5us throttle clock */
@@ -131,8 +128,6 @@ static void setup_pm(device_t dev)
/* GP2 Timer Counter */
pci_write_config8(dev, 0x99, 0xfb);
- /* GP3 Timer Counter */
- //pci_write_config8(dev, 0x9a, 0x20);
/* Multi Function Select 1 */
pci_write_config8(dev, 0xe4, 0x00);
@@ -178,16 +173,6 @@ static void setup_pm(device_t dev)
* Will work for C3 and for FID/VID change.
*/
outb(0x1, VX800_ACPI_IO_BASE + 0x11);
-/*
- outw(0x0, 0x424);
- outw(0x0, 0x42a);
- outw(0x1, 0x42c);
- outl(0x0, 0x434);
- outl(0x01, 0x438);
- outb(0x0, 0x442);
- outl(0xffff7fff, 0x448);
- outw(0x001, 0x404);
-*/
}
static void S3_ps2_kb_ms_wakeup(struct device *dev)
@@ -234,7 +219,6 @@ static void vx800_sb_init(struct device *dev)
pci_write_config8(dev, 0x6C, enables);
// Map 4MB of FLASH into the address space
-// pci_write_config8(dev, 0x41, 0x7f);
// Set bit 6 of 0x40, because Award does it (IO recovery time)
// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
@@ -255,7 +239,6 @@ static void vx800_sb_init(struct device *dev)
pci_write_config8(dev, 0x59, 0x80);
/* Set 0x5b to 0x01 to match Award */
- //pci_write_config8(dev, 0x5b, 0x01);
enables = pci_read_config8(dev, 0x5b);
enables |= 0x01;
pci_write_config8(dev, 0x5b, enables);
@@ -264,7 +247,6 @@ static void vx800_sb_init(struct device *dev)
pci_write_config8(dev, 0x48, 0x0c);
/* Set 0x58 to 0x42 APIC and RTC. */
- //pci_write_config8(dev, 0x58, 0x42); this cmd cause the irq0 can not be triggerd,since bit 5 was set to 0.
enables = pci_read_config8(dev, 0x58);
enables |= 0x41; //
pci_write_config8(dev, 0x58, enables);
diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c
index 6391321..e6ec3b5 100644
--- a/src/northbridge/via/vx800/northbridge.c
+++ b/src/northbridge/via/vx800/northbridge.c
@@ -38,22 +38,6 @@ static void memctrl_init(device_t dev)
/*
set VGA in uma_ram_setting.c, not in this function.
*/
-#if 0
- pci_write_config8(dev, 0x85, 0x20);
- pci_write_config8(dev, 0x86, 0x2d);
-
- /* Set up VGA timers */
- pci_write_config8(dev, 0xa2, 0x44);
-
- /* Enable VGA with a 32mb framebuffer */
- pci_write_config16(dev, 0xa0, 0xd000);
-
- pci_write_config16(dev, 0xa4, 0x0010);
-
- //b0: 60 aa aa 5a 0f 00 00 00 08
- pci_write_config16(dev, 0xb0, 0xaa00);
- pci_write_config8(dev, 0xb8, 0x08);
-#endif
}
static const struct device_operations memctrl_operations = {
diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c
index bf59093..46c2782 100644
--- a/src/northbridge/via/vx800/uma_ram_setting.c
+++ b/src/northbridge/via/vx800/uma_ram_setting.c
@@ -94,23 +94,16 @@ void SetUMARam(void)
//GMINT and GFX relatate
//note Bit 3 VGA Enable
pci_write_config8(MEMCTRL, 0xa7, 0x8c);
- // ByteVal = 0x4c;
//GMINT Misc.1
- //pci_write_config8(MEMCTRL, 0xb0, 0x80);
-
- //pci_write_config8(MEMCTRL, 0xb1, 0xaa);
//AGPCINT MISC
- //pci_write_config8(MEMCTRL, 0xb2, 0x82);
- //ByteVal = 0x8A;
//GMINT MISC.2
//disable read pass write
pci_write_config8(MEMCTRL, 0xb3, 0x9A);
//EPLL Register
- //pci_write_config8(MEMCTRL, 0xb4, 0x04);
//enable CHA and CHB merge mode
pci_write_config8(MEMCTRL, 0xde, 0x06);
@@ -133,17 +126,12 @@ void SetUMARam(void)
ByteVal = (ByteVal & 0x8f) | (SLD0F3Val << 4);
pci_write_config8(MEMCTRL, 0xa1, ByteVal);
-// vga_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VGA, 0);
-
//RxB2 may be for S.L. and RxB1 may be for L. L.
// It is different from Spec.
ByteVal = SLD1F0Val;
pci_write_config8(vga_dev, 0xb2, ByteVal);
//set M1 size
- //ByteVal = pci_read_config8(MEMCTRL, 0xa3);
- //ByteVal = 0x02;
- //pci_write_config8(MEMCTRL, 0xa3, ByteVal);
PRINT_DEBUG_MEM("UMA setting - 3\n");
@@ -177,7 +165,6 @@ void SetUMARam(void)
//enable GFx memory space access control for S.L and mmio
ByteVal = pci_read_config8(d0f0_dev, 0xD4);
ByteVal |= 0x03;
- //ByteVal |= 0x01;
pci_write_config8(d0f0_dev, 0xD4, ByteVal);
//enable Base VGA 16 Bits Decode
@@ -189,15 +176,12 @@ void SetUMARam(void)
//set VGA memory selection
ByteVal = pci_read_config8(vga_dev, 0xb0);
ByteVal &= 0xF8;
- //ByteVal |= 0x01;
ByteVal |= 0x03;
pci_write_config8(vga_dev, 0xb0, ByteVal);
//set LL size
//enable memory access to SL,MMIO,LL and IO to 3B0~3BB,3C0 ~3DF
- //ByteVal = 0x03;
- //pci_write_config8(d0f0_dev, 0xc0, ByteVal);
//Turn on Graphic chip IO port port access
ByteVal = inb(0x03C3);
@@ -216,9 +200,6 @@ void SetUMARam(void)
ByteVal = inb(0x03CC);
ByteVal |= 0x03;
outb(ByteVal, 0x03C2);
- // ByteVal = inb(0x03C2);
- // ByteVal |= 0x01;
- // outb(ByteVal,0x03C2);
#if 1 //bios porting guide has no this two defination: 3d on 3d4/3d5 and 39 on 3c4/3c5
//set frequence 0x3D5.3d[7:4]
@@ -329,101 +310,8 @@ void SetUMARam(void)
ByteVal = (ByteVal & 0xE5) | 0x1A;
outb(ByteVal, 0x03d5);
-#if 0
- u8 table3c43c5[0x70] = {
- 0x03, 0x01, 0x0F, 0x00, 0x06, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x01, 0x78, 0x00, 0x00, 0x00, 0xBE, 0x20, 0x7F,
- 0x60, 0x7F, 0x08, 0x31, 0xCC, 0x00, 0x01, 0x00,
- 0x00, 0x18, 0x10, 0x00, 0x00, 0x00, 0x3D, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x04, 0xF3, 0xFF, 0xFC,
- 0xF8, 0x0C, 0x00, 0x00, 0x40, 0x06, 0x11, 0x22,
- 0x51, 0x10, 0x00, 0x01, 0x19, 0x0C, 0x00, 0xFF,
- 0x38, 0x40, 0x30, 0xFF, 0x70, 0x8C, 0x85, 0x9D,
- 0x80, 0x05, 0x54, 0x90, 0x03, 0x30, 0x00, 0x5F,
- 0x1F, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00,
- 0x06, 0xDF, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x40, 0x20, 0x00, 0x20, 0x20,
- 0xE0, 0x20, 0xD0, 0x3F, 0x00, 0xE0, 0x00, 0x00
- };
- u8 table3d43d5[0x88] = {
- 0x7F, 0x63, 0x63, 0x83, 0x69, 0x19, 0x72, 0xE0,
- 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x58, 0x9C, 0x57, 0x90, 0x00, 0x57, 0x73, 0xE3,
- 0x57, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x0C, 0x00, 0x11, 0x06, 0x00, 0x20, 0x01, 0x34,
- 0xEE, 0x74, 0x01, 0x01, 0x08, 0x84, 0x00, 0x00,
- 0x00, 0xF3, 0x40, 0x90, 0x00, 0x00, 0x00, 0x01,
- 0x00, 0x12, 0x00, 0x02, 0x00, 0x00, 0x10, 0x00,
- 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D,
- 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x9D, 0x9D, 0x10,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x9D, 0x9D, 0x9D,
- 0x9D, 0x9D, 0x9D, 0x9D, 0x00, 0x9D, 0x1D, 0x00,
- 0x00, 0x00, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D,
- 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D,
- };
-
- u8 table3c0space[0xc0] = {
- 0x11, 0x00, 0x10, 0x01, 0x26, 0x3D, 0xFF, 0x00,
- 0x10, 0x3F, 0x00, 0x00, 0x2F, 0x00, 0x22, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x50, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- };
-
- //for (i = 0;i < 0xc0;i++)
- for (i = 0; i < 0x40; i++)
- {
- outb(table3c0space[i], 0x03c0 + i);
- }
-
- for (i = 0; i < 0x70; i++) {
- outb(i, 0x03c4);
- outb(table3c43c5[i], 0x03c5);
- }
- for (i = 0; i < 0x88; i++) {
- outb(i, 0x03d4);
- outb(table3d43d5[i], 0x03d5);
- }
-
- outb(0x92, 0x03d4);
- outb(0x80, 0x03d5);
-
- outb(0xa3, 0x03d4);
- outb(0x00, 0x03d5);
-
- outb(0xe8, 0x03d4);
- outb(0x40, 0x03d5);
-#endif
-
// 3d4 3d freq
// IO Port / Index: 3X5.3D
// Scratch Pad Register 4
-// outb(0x39,0x03c4);
-// outb(1 << SLD0F3Val ,0x03c5);
-//
#endif
-
}
diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c
index 664e915..70a916f 100644
--- a/src/northbridge/via/vx800/vga.c
+++ b/src/northbridge/via/vx800/vga.c
@@ -134,10 +134,6 @@ static void write_protect_vgabios(void)
PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0);
if (dev)
pci_write_config8(dev, 0x80, 0xff);
- /*vx855 no th 0x61 reg */
- /*dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VLINK, 0);
- //if (dev)
- // pci_write_config8(dev, 0x61, 0xff); */
}
#endif
@@ -166,15 +162,6 @@ static void vga_init(device_t dev)
reg8 = reg8 | 2;
outb(reg8, 0x92);
- //*
- //pci_write_config8(dev, 0x04, 0x07);
- //pci_write_config32(dev,0x10, 0xa0000008);
- //pci_write_config32(dev,0x14, 0xdd000000);
- pci_write_config32(dev, 0x10, VIACONFIG_VGA_PCI_10);
- pci_write_config32(dev, 0x14, VIACONFIG_VGA_PCI_14);
- pci_write_config8(dev, 0x3c, 0x0a); //same with vx855_lpc.c
- //*/
-
printk(BIOS_DEBUG, "Initializing VGA...\n");
pci_dev_init(dev);
@@ -192,13 +179,6 @@ static void vga_init(device_t dev)
reg8 |= (0x3 << 4);
outb(0x3d, CRTM_INDEX);
outb(reg8, CRTM_DATA);
-
-#if 0
- /* Set framebuffer size to CONFIG_VIDEO_MB mb */
- reg8 = (CONFIG_VIDEO_MB/4);
- outb(0x39, SR_INDEX);
- outb(reg8, SR_DATA);
-#endif
}
}
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