[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Add soc core init
Ravishankar Sarawadi (ravishankar.sarawadi@intel.com)
gerrit at coreboot.org
Thu Oct 6 00:31:20 CEST 2016
Ravishankar Sarawadi (ravishankar.sarawadi at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16587
-gerrit
commit 1fcacb7147a7cbe822808af3fd76e31578a70ce7
Author: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
Date: Fri Sep 9 14:08:50 2016 -0700
soc/apollolake: Add soc core init
Skip FSP initiated core/MP init.
Add soc core init to setup following feature MSRs:
1. C-states
2. IO/Mwait redirection
BUG=chrome-os-partner:56922
BRANCH=None
TEST=Use iotools rdmsr and 'powertop' to check
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
Change-Id: I97c3d82f654be30a0d2d88cb68c8212af3d6f767
---
src/soc/intel/apollolake/chip.c | 1 +
src/soc/intel/apollolake/cpu.c | 21 ++++++++++++++++++++-
src/soc/intel/apollolake/include/soc/cpu.h | 13 +++++++++++++
3 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index eeac6ce..adc578d 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -416,6 +416,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2;
silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
+ silconfig->SkipMpInit = 1;
/* Disable monitor mwait since it is broken due to a hardware bug without a fix */
silconfig->MonitorMwaitEnable = 0;
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index f3cf050..a1a7c17 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -25,11 +25,30 @@
#include <cpu/x86/mtrr.h>
#include <device/device.h>
#include <device/pci.h>
+#include <reg_script.h>
#include <soc/cpu.h>
#include <soc/smm.h>
+static const struct reg_script core_msr_script[] = {
+ /* Enable C-state and IO/MWAIT redirect */
+ REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL,
+ (PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK
+ | IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK), 0),
+ /* Power Management I/O base address for I/O trapping to C-states */
+ REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE, 0x50414),
+ /* Disable C1E */
+ REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
+ REG_SCRIPT_END
+};
+
+static void soc_core_init(device_t cpu)
+{
+ /* Set core MSRs */
+ reg_script_run(core_msr_script);
+}
+
static struct device_operations cpu_dev_ops = {
- .init = DEVICE_NOOP,
+ .init = soc_core_init,
};
static struct cpu_device_id cpu_table[] = {
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index 22412af..3d682a0 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -40,6 +40,19 @@ void apollolake_init_cpus(struct device *dev);
#define MSR_PKG_POWER_SKU_UNIT 0x606
+/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */
+#define PKG_C_STATE_LIMIT_C2_MASK 0x2
+/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/
+#define CORE_C_STATE_LIMIT_C10_MASK 0x70
+/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */
+#define IO_MWAIT_REDIRECT_MASK 0x400
+/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */
+#define CST_CFG_LOCK_MASK 0x8000
+
+#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
+#define MSR_PMG_IO_CAPTURE_BASE 0xe4
+#define MSR_POWER_CTL 0x1fc
+
#define MSR_L2_QOS_MASK(reg) (0xd10 + reg)
#define MSR_IA32_PQR_ASSOC 0xc8f
/* MSR bits 33:32 encode slot number 0-3 */
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