[coreboot-gerrit] New patch to review for coreboot: soc/intel/skylake: Handle platform global reset

[Rizwan Qureshi (rizwan.qureshi@intel.com)]

Rizwan Qureshi (rizwan.qureshi at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16903

-gerrit

commit 90a30e528076e873fba1823028d9b5f24fa20dc6
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Fri Aug 19 13:17:36 2016 +0530

    soc/intel/skylake: Handle platform global reset
    
    In FSP1.1 all the platform resets including global was handled
    on its own without any intervention from coreboot.
    In FSP2.0, any reset required will be notified to coreboot
    and it is expected that coreboot will perform platform reset.
    
    Hence, implement platform global reset hooks in coreboot. If Intel
    ME is in non ERROR state then MEI message will able to perform
    global reset else force global reset by writing 0x6 or 0xE to
    0xCF9 port with PCH ETR3 register bit [20] set.
    
    BUG=none
    BRANCH=none
    TEST=Verified platform global reset is working with MEI
    message or writing to PCH ETR3.
    
    Change-Id: I57e55caa6d20b15644bac686be8734d9652f21e5
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
---
 src/soc/intel/skylake/reset.c | 35 ++++++++++++++++++++++++++++++++++-
 1 file changed, 34 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c
index 638a151..0994762 100644
--- a/src/soc/intel/skylake/reset.c
+++ b/src/soc/intel/skylake/reset.c
@@ -16,13 +16,46 @@
 #include <console/console.h>
 #include <fsp/util.h>
 #include <reset.h>
+#include <soc/me.h>
+#include <soc/pm.h>
+#include <timer.h>
+
+static void do_force_global_reset(void)
+{
+	u32 reg32;
+	/*PMC Controller Device 0x1F, Func 02*/
+	uint8_t *pmc_regs;
+
+	/*
+	 * BIOS should ensure it does a global reset
+	 * to reset both host and Intel ME by setting
+	 * PCH PMC [B0:D31:F2 register offset 0x1048 bit 20]
+	 */
+	pmc_regs = pmc_mmio_regs();
+	reg32 = read32(pmc_regs + ETR3);
+	reg32 |= ETR3_CF9GR;
+	write32(pmc_regs + ETR3, reg32);
+
+	/* Now BIOS can write 0x06 or 0x0E to 0xCF9 port
+	 * to global reset platform */
+	hard_reset();
+}
+
+void global_reset(void)
+{
+	if (send_global_reset() != 0) {
+		/* If ME unable to reset platform then
+		 * force global reset using PMC CF9GR register*/
+		do_force_global_reset();
+	}
+}
 
 void chipset_handle_reset(uint32_t status)
 {
 	switch(status) {
 	case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
 		printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
-		hard_reset();
+		global_reset();
 		break;
 	default:
 		printk(BIOS_ERR, "unhandled reset type %x\n", status);