[coreboot-gerrit] Patch merged into coreboot/master: arm64: Use 'payload' format for ATF instead of 'stage'

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 7ae73fc3a07fed94846054dda30d0be67245e9c3
Author: Simon Glass <sjg at chromium.org>
Date:   Sat Aug 27 12:18:38 2016 -0600

    arm64: Use 'payload' format for ATF instead of 'stage'
    
    Switch the BL31 (ARM Trusted Firmware) format to payload so that it can
    have multiple independent segments. This also requires disabling the region
    check since SRAM is currently faulted by that check.
    
    This has been tested with Rockchip's pending change:
    
    https://chromium-review.googlesource.com/#/c/368592/3
    
    with the patch mentioned on the bug at #13.
    
    BUG=chrome-os-partner:56314
    BRANCH=none
    TEST=boot on gru and see that BL31 loads and runs. Im not sure if it is
    correct though:
    CBFS: Locating 'fallback/payload'
    CBFS: Found @ offset 1b440 size 15a75
    Loading segment from ROM address 0x0000000000100000
      code (compression=1)
      New segment dstaddr 0x18104800 memsize 0x117fbe0 srcaddr 0x100038 filesize 0x15a3d
    Loading segment from ROM address 0x000000000010001c
      Entry Point 0x0000000018104800
    Loading Segment: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d
    lb: [0x0000000000300000, 0x0000000000320558)
    Post relocation: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d
    using LZMA
    [ 0x18104800, 18137d90, 0x192843e0) <- 00100038
    Clearing Segment: addr: 0x0000000018137d90 memsz: 0x000000000114c650
    dest 0000000018104800, end 00000000192843e0, bouncebuffer ffffffffffffffff
    Loaded segments
    BS: BS_PAYLOAD_LOAD times (us): entry 0 run 125150 exit 1
    Jumping to boot code at 0000000018104800(00000000f7eda000)
    CPU0: stack: 00000000ff8ec000 - 00000000ff8f0000, lowest used address 00000000ff8ef3d0, stack used: 3120 bytes
    CBFS: 'VBOOT' located CBFS at [402000:44cc00)
    CBFS: Locating 'fallback/bl31'
    CBFS: Found @ offset 10ec0 size 8d0c
    Loading segment from ROM address 0x0000000000100000
      code (compression=1)
      New segment dstaddr 0x10000 memsize 0x40000 srcaddr 0x100054 filesize 0x8192
    Loading segment from ROM address 0x000000000010001c
      code (compression=1)
      New segment dstaddr 0xff8d4000 memsize 0x1f50 srcaddr 0x1081e6 filesize 0xb26
    Loading segment from ROM address 0x0000000000100038
      Entry Point 0x0000000000010000
    Loading Segment: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192
    lb: [0x0000000000300000, 0x0000000000320558)
    Post relocation: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192
    using LZMA
    [ 0x00010000, 00035708, 0x00050000) <- 00100054
    Clearing Segment: addr: 0x0000000000035708 memsz: 0x000000000001a8f8
    dest 0000000000010000, end 0000000000050000, bouncebuffer ffffffffffffffff
    Loading Segment: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26
    lb: [0x0000000000300000, 0x0000000000320558)
    Post relocation: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26
    using LZMA
    [ 0xff8d4000, ff8d5f50, 0xff8d5f50) <- 001081e6
    dest 00000000ff8d4000, end 00000000ff8d5f50, bouncebuffer ffffffffffffffff
    Loaded segments
    INFO:    plat_rockchip_pmusram_prepare pmu: code d2bfe625,d2bfe625,80
    INFO:    plat_rockchip_pmusram_prepare pmu: code 0xff8d4000,0x50000,3364
    INFO:    plat_rockchip_pmusram_prepare: data 0xff8d4d28,0xff8d4d24,4648
    NOTICE:  BL31: v1.2(debug):
    NOTICE:  BL31: Built : Sun Sep  4 22:36:16 UTC 2016
    INFO:    GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3
    INFO:    plat_rockchip_pmu_init(1189): pd status 3e
    INFO:    BL31: Initializing runtime services
    INFO:    BL31: Preparing for EL3 exit to normal world
    INFO:    Entry point address = 0x18104800
    INFO:    SPSR = 0x8
    
    Change-Id: Ie2484d122a603f1c7b7082a1de3f240aa6e6d540
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 8c1d75bff6e810a39776048ad9049ec0a9c5d94e
    Original-Change-Id: I2d60e5762f8377e43835558f76a3928156acb26c
    Original-Signed-off-by: Simon Glass <sjg at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/376849
    Original-Commit-Ready: Simon Glass <sjg at google.com>
    Original-Tested-by: Simon Glass <sjg at google.com>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Reviewed-on: https://review.coreboot.org/16706
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/16706 for details.

-gerrit